mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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3bb9948921
Add compatible strings for the MediaTek Dimensity 9400 MT6991 and for the MT8196 Chromebook SoC, having the same PWM IP v3.0.2. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250623120118.109170-2-angelogioacchino.delregno@collabora.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
101 lines
2.4 KiB
YAML
101 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PWM Controller
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maintainers:
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- John Crispin <john@phrozen.org>
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2712-pwm
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- mediatek,mt6795-pwm
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- mediatek,mt6991-pwm
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- mediatek,mt7622-pwm
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- mediatek,mt7623-pwm
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- mediatek,mt7628-pwm
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- mediatek,mt7629-pwm
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- mediatek,mt7981-pwm
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- mediatek,mt7986-pwm
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- mediatek,mt7988-pwm
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- mediatek,mt8183-pwm
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- mediatek,mt8365-pwm
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- mediatek,mt8516-pwm
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- items:
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- enum:
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- mediatek,mt8195-pwm
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- const: mediatek,mt8183-pwm
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- items:
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- enum:
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- mediatek,mt8196-pwm
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- const: mediatek,mt6991-pwm
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reg:
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maxItems: 1
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"#pwm-cells":
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const: 2
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interrupts:
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maxItems: 1
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clocks:
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minItems: 2
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maxItems: 10
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clock-names:
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description:
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This controller needs two input clocks for its core and one
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clock for each PWM output.
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minItems: 2
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items:
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- const: top
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- const: main
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- const: pwm1
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- const: pwm2
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- const: pwm3
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- const: pwm4
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- const: pwm5
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- const: pwm6
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- const: pwm7
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- const: pwm8
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt2712-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pwm0: pwm@11006000 {
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compatible = "mediatek,mt2712-pwm";
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reg = <0x11006000 0x1000>;
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#pwm-cells = <2>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM>,
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<&pericfg CLK_PERI_PWM0>, <&pericfg CLK_PERI_PWM1>,
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<&pericfg CLK_PERI_PWM2>, <&pericfg CLK_PERI_PWM3>,
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<&pericfg CLK_PERI_PWM4>, <&pericfg CLK_PERI_PWM5>,
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<&pericfg CLK_PERI_PWM6>, <&pericfg CLK_PERI_PWM7>;
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clock-names = "top", "main",
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"pwm1", "pwm2",
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"pwm3", "pwm4",
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"pwm5", "pwm6",
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"pwm7", "pwm8";
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};
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