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01b8f5b53e
This adds the support for 2 others MIPS based VCore III SoCs: Luton and Jaguar2. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
20 lines
472 B
Plaintext
20 lines
472 B
Plaintext
Microsemi Ocelot reset controller
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The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
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SoC core.
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The reset registers are both present in the MSCC vcoreiii MIPS and
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microchip Sparx5 armv8 SoC's.
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Required Properties:
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- compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
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"mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
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Example:
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reset@1070008 {
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compatible = "mscc,ocelot-chip-reset";
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reg = <0x1070008 0x4>;
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};
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