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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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912275c325
'HDP' stands for Hardware Debug Port, it is an hardware block in STMicrolectronics' MPUs that let the user decide which internal SoC's signal to observe. It provides 8 ports and for each port there is up to 16 different signals that can be output. Signals are different for each MPU. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Link: https://lore.kernel.org/20250711-hdp-upstream-v7-1-faeecf7aaee1@foss.st.com [Fixed up Clement's new email address] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
188 lines
9.7 KiB
YAML
188 lines
9.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) STMicroelectronics 2025.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STM32 Hardware Debug Port Mux/Config
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maintainers:
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- Clément LE GOFFIC <legoffic.clement@gmail.com>
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description:
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STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP).
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It allows to output internal signals on SoC's GPIO.
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properties:
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compatible:
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enum:
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- st,stm32mp131-hdp
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- st,stm32mp151-hdp
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- st,stm32mp251-hdp
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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patternProperties:
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"^hdp[0-7]-pins$":
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type: object
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$ref: pinmux-node.yaml#
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additionalProperties: false
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properties:
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pins:
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pattern: '^HDP[0-7]$'
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function: true
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required:
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- function
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- pins
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allOf:
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- $ref: pinctrl.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp131-hdp
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then:
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patternProperties:
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"^hdp[0-7]-pins$":
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properties:
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function:
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enum: [ pwr_pwrwake_sys, pwr_stop_forbidden, pwr_stdby_wakeup, pwr_encomp_vddcore,
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bsec_out_sec_niden, aiec_sys_wakeup, none, ddrctrl_lp_req,
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pwr_ddr_ret_enable_n, dts_clk_ptat, sram3ctrl_tamp_erase_act, gpoval0,
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pwr_sel_vth_vddcpu, pwr_mpu_ram_lowspeed, ca7_naxierrirq, pwr_okin_mr,
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bsec_out_sec_dbgen, aiec_c1_wakeup, rcc_pwrds_mpu, ddrctrl_dfi_ctrlupd_req,
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ddrctrl_cactive_ddrc_asr, sram3ctrl_hw_erase_act, nic400_s0_bready, gpoval1,
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pwr_pwrwake_mpu, pwr_mpu_clock_disable_ack, ca7_ndbgreset_i,
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bsec_in_rstcore_n, bsec_out_sec_bsc_dis, ddrctrl_dfi_init_complete,
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ddrctrl_perf_op_is_refresh, ddrctrl_gskp_dfi_lp_req, sram3ctrl_sw_erase_act,
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nic400_s0_bvalid, gpoval2, pwr_sel_vth_vddcore, pwr_mpu_clock_disable_req,
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ca7_npmuirq0, ca7_nfiqout0, bsec_out_sec_dftlock, bsec_out_sec_jtag_dis,
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rcc_pwrds_sys, sram3ctrl_tamp_erase_req, ddrctrl_stat_ddrc_reg_selfref_type0,
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dts_valobus1_0, dts_valobus2_0, tamp_potential_tamp_erfcfg, nic400_s0_wready,
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nic400_s0_rready, gpoval3, pwr_stop2_active, ca7_nl2reset_i,
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ca7_npreset_varm_i, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
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eth1_out_pmt_intr_o, eth2_out_pmt_intr_o, ddrctrl_stat_ddrc_reg_selfref_type1,
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ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, tamp_nreset_sram_ercfg,
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nic400_s0_wlast, nic400_s0_rlast, gpoval4, ca7_standbywfil2,
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pwr_vth_vddcore_ack, ca7_ncorereset_i, ca7_nirqout0, bsec_in_pwrok,
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bsec_out_sec_deviceen, eth1_out_lpi_intr_o, eth2_out_lpi_intr_o,
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ddrctrl_cactive_ddrc, ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2,
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pka_pka_itamp_out, nic400_s0_wvalid, nic400_s0_rvalid, gpoval5,
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ca7_standbywfe0, pwr_vth_vddcpu_ack, ca7_evento, bsec_in_tamper_det,
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bsec_out_sec_spniden, eth1_out_mac_speed_o1, eth2_out_mac_speed_o1,
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ddrctrl_csysack_ddrc, ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3,
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saes_tamper_out, nic400_s0_awready, nic400_s0_arready, gpoval6,
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ca7_standbywfi0, pwr_rcc_vcpu_rdy, ca7_eventi, ca7_dbgack0, bsec_out_fuse_ok,
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bsec_out_sec_spiden, eth1_out_mac_speed_o0, eth2_out_mac_speed_o0,
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ddrctrl_csysreq_ddrc, ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4,
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rng_tamper_out, nic400_s0_awavalid, nic400_s0_aravalid, gpoval7 ]
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp151-hdp
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then:
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patternProperties:
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"^hdp[0-7]-pins$":
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properties:
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function:
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enum: [ pwr_pwrwake_sys, cm4_sleepdeep, pwr_stdby_wkup, pwr_encomp_vddcore,
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bsec_out_sec_niden, none, rcc_cm4_sleepdeep, gpu_dbg7, ddrctrl_lp_req,
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pwr_ddr_ret_enable_n, dts_clk_ptat, gpoval0, pwr_pwrwake_mcu, cm4_halted,
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ca7_naxierrirq, pwr_okin_mr, bsec_out_sec_dbgen, exti_sys_wakeup,
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rcc_pwrds_mpu, gpu_dbg6, ddrctrl_dfi_ctrlupd_req, ddrctrl_cactive_ddrc_asr,
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gpoval1, pwr_pwrwake_mpu, cm4_rxev, ca7_npmuirq1, ca7_nfiqout1,
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bsec_in_rstcore_n, exti_c2_wakeup, rcc_pwrds_mcu, gpu_dbg5,
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ddrctrl_dfi_init_complete, ddrctrl_perf_op_is_refresh,
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ddrctrl_gskp_dfi_lp_req, gpoval2, pwr_sel_vth_vddcore, cm4_txev, ca7_npmuirq0,
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ca7_nfiqout0, bsec_out_sec_dftlock, exti_c1_wakeup, rcc_pwrds_sys, gpu_dbg4,
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ddrctrl_stat_ddrc_reg_selfref_type0, ddrctrl_cactive_1, dts_valobus1_0,
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dts_valobus2_0, gpoval3, pwr_mpu_pdds_not_cstbydis, cm4_sleeping, ca7_nreset1,
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ca7_nirqout1, bsec_out_sec_dften, bsec_out_sec_dbgswenable,
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eth_out_pmt_intr_o, gpu_dbg3, ddrctrl_stat_ddrc_reg_selfref_type1,
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ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, gpoval4, ca7_standbywfil2,
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pwr_vth_vddcore_ack, ca7_nreset0, ca7_nirqout0, bsec_in_pwrok,
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bsec_out_sec_deviceen, eth_out_lpi_intr_o, gpu_dbg2, ddrctrl_cactive_ddrc,
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ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, gpoval5,
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ca7_standbywfi1, ca7_standbywfe1, ca7_evento, ca7_dbgack1,
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bsec_out_sec_spniden, eth_out_mac_speed_o1, gpu_dbg1, ddrctrl_csysack_ddrc,
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ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, gpoval6,
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ca7_standbywfi0, ca7_standbywfe0, ca7_dbgack0, bsec_out_fuse_ok,
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bsec_out_sec_spiden, eth_out_mac_speed_o0, gpu_dbg0, ddrctrl_csysreq_ddrc,
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ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, gpoval7 ]
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- if:
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properties:
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compatible:
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contains:
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const: st,stm32mp251-hdp
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then:
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patternProperties:
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"^hdp[0-7]-pins$":
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properties:
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function:
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enum: [ pwr_pwrwake_sys, cpu2_sleep_deep, bsec_out_tst_sdr_unlock_or_disable_scan,
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bsec_out_nidenm, bsec_out_nidena, cpu2_state_0, rcc_pwrds_sys, gpu_dbg7,
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ddrss_csysreq_ddrc, ddrss_dfi_phyupd_req, cpu3_sleep_deep,
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d2_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_0,
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pcie_usb_cxpl_debug_info_ei_8, d3_state_0, gpoval0, pwr_pwrwake_cpu2,
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cpu2_halted, cpu2_state_1, bsec_out_dbgenm, bsec_out_dbgena, exti1_sys_wakeup,
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rcc_pwrds_cpu2, gpu_dbg6, ddrss_csysack_ddrc, ddrss_dfi_phymstr_req,
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cpu3_halted, d2_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_1,
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pcie_usb_cxpl_debug_info_ei_9, d3_state_1, gpoval1, pwr_pwrwake_cpu1,
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cpu2_rxev, cpu1_npumirq1, cpu1_nfiqout1, bsec_out_shdbgen, exti1_cpu2_wakeup,
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rcc_pwrds_cpu1, gpu_dbg5, ddrss_cactive_ddrc, ddrss_dfi_lp_req, cpu3_rxev,
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hpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_2,
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pcie_usb_cxpl_debug_info_ei_10, d3_state_2, gpoval2, pwr_sel_vth_vddcpu,
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cpu2_txev, cpu1_npumirq0, cpu1_nfiqout0, bsec_out_ddbgen, exti1_cpu1_wakeup,
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cpu3_state_0, gpu_dbg4, ddrss_mcdcg_en, ddrss_dfi_freq_0, cpu3_txev,
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hpdma2_clk_bus_req, pcie_usb_cxpl_debug_info_ei_3,
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pcie_usb_cxpl_debug_info_ei_11, d1_state_0, gpoval3, pwr_sel_vth_vddcore,
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cpu2_sleeping, cpu1_evento, cpu1_nirqout1, bsec_out_spnidena, exti2_d3_wakeup,
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eth1_out_pmt_intr_o, gpu_dbg3, ddrss_dphycg_en, ddrss_obsp0, cpu3_sleeping,
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hpdma3_clk_bus_req, pcie_usb_cxpl_debug_info_ei_4,
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pcie_usb_cxpl_debug_info_ei_12, d1_state_1, gpoval4, cpu1_standby_wfil2,
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none, cpu1_nirqout0, bsec_out_spidena, exti2_cpu3_wakeup, eth1_out_lpi_intr_o,
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gpu_dbg2, ddrctrl_dfi_init_start, ddrss_obsp1, cpu3_state_1,
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d3_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_5,
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pcie_usb_cxpl_debug_info_ei_13, d1_state_2, gpoval5, cpu1_standby_wfi1,
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cpu1_standby_wfe1, cpu1_halted1, cpu1_naxierrirq, bsec_out_spnidenm,
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exti2_cpu2_wakeup, eth2_out_pmt_intr_o, gpu_dbg1, ddrss_dfi_init_complete,
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ddrss_obsp2, d2_state_0, d3_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_6,
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pcie_usb_cxpl_debug_info_ei_14, cpu1_state_0, gpoval6, cpu1_standby_wfi0,
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cpu1_standby_wfe0, cpu1_halted0, bsec_out_spidenm, exti2_cpu1__wakeup,
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eth2_out_lpi_intr_o, gpu_dbg0, ddrss_dfi_ctrlupd_req, ddrss_obsp3, d2_state_1,
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lpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_7,
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pcie_usb_cxpl_debug_info_ei_15, cpu1_state_1, gpoval7 ]
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required:
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- compatible
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- reg
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/stm32mp1-clks.h>
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pinctrl@54090000 {
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compatible = "st,stm32mp151-hdp";
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reg = <0x54090000 0x400>;
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clocks = <&rcc HDP>;
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pinctrl-names = "default";
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pinctrl-0 = <&hdp2_gpo>;
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hdp2_gpo: hdp2-pins {
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function = "gpoval2";
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pins = "HDP2";
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};
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};
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