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fd7dac34fd
Document the Top Level Mode Multiplexer on the Milos Platform. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20250702-sm7635-pinctrl-v2-1-c138624b9924@fairphone.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
134 lines
4.1 KiB
YAML
134 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,milos-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Milos TLMM block
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maintainers:
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- Luca Weiss <luca.weiss@fairphone.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm Milos SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,milos-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 84
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gpio-line-names:
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maxItems: 167
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-milos-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-milos-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-milos-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-7])$"
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- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
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audio_ext_mclk1, audio_ref_clk, cam_mclk, cci_async_in0,
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cci_i2c_scl, cci_i2c_sda, cci_timer, coex_uart1_rx,
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coex_uart1_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail,
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ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot,
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egpio, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2s0_data0,
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i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
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mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
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mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req_n,
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pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,
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prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
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qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss,
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qlink1_enable, qlink1_request, qlink1_wmss, qspi0, qup0_se0,
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qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, qup0_se6,
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qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5,
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qup1_se6, resout_gpio_n, sd_write_protect, sdc1_clk, sdc1_cmd,
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sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data,
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sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tgu_ch0_trigout,
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tgu_ch1_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
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tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
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uim0_present, uim0_reset, uim1_clk_mira, uim1_clk_mirb,
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uim1_data_mira, uim1_data_mirb, uim1_present_mira,
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uim1_present_mirb, uim1_reset_mira, uim1_reset_mirb, usb0_hs,
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usb0_phy_ps, vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw,
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wcn_sw_ctrl ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f100000 {
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compatible = "qcom,milos-tlmm";
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reg = <0x0f100000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 168>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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qup-uart5-default-state {
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pins = "gpio25", "gpio26";
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function = "qup0_se5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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...
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