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b225010185
Add the new binding document for pinctrl on MediaTek mt8189. Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/20250711094513.17073-2-ot_cathy.xu@mediatek.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
214 lines
6.1 KiB
YAML
214 lines
6.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT8189 Pin Controller
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maintainers:
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- Lei Xue <lei.xue@mediatek.com>
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- Cathy Xu <ot_cathy.xu@mediatek.com>
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description:
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The MediaTek's MT8189 Pin controller is used to control SoC pins.
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properties:
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compatible:
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const: mediatek,mt8189-pinctrl
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reg:
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items:
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- description: gpio base
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- description: lm group IO
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- description: rb0 group IO
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- description: rb1 group IO
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- description: bm0 group IO
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- description: bm1 group IO
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- description: bm2 group IO
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- description: lt0 group IO
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- description: lt1 group IO
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- description: rt group IO
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- description: eint0 group IO
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- description: eint1 group IO
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- description: eint2 group IO
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- description: eint3 group IO
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- description: eint4 group IO
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reg-names:
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items:
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- const: base
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- const: lm
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- const: rb0
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- const: rb1
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- const: bm0
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- const: bm1
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- const: bm2
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- const: lt0
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- const: lt1
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- const: rt
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- const: eint0
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- const: eint1
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- const: eint2
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- const: eint3
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- const: eint4
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interrupts:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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gpio-controller: true
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'#gpio-cells':
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const: 2
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gpio-ranges:
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maxItems: 1
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gpio-line-names: true
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# PIN CONFIGURATION NODES
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patternProperties:
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'-pins$':
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type: object
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additionalProperties: false
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patternProperties:
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'^pins':
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type: object
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$ref: /schemas/pinctrl/pincfg-node.yaml
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additionalProperties: false
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description:
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A pinctrl node should contain at least one subnode representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, pullups, drive strength, input enable/disable and input
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schmitt.
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properties:
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pinmux:
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description:
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Integer array, represents gpio pin number and mux setting.
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Supported pin number and mux varies for different SoCs, and are
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defined as macros in arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h
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directly, for this SoC.
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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bias-pull-down:
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oneOf:
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- type: boolean
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- enum: [100, 101, 102, 103]
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description: mt8189 pull down PUPD/R0/R1 type define value.
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- enum: [75000, 5000]
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description: mt8189 pull down RSEL type si unit value(ohm).
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description: |
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For pull down type is normal, it doesn't need add R1R0 define
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and resistance value.
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For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
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set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
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"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
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"MTK_PUPD_SET_R1R0_11" define in mt8189.
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For pull down type is PD/RSEL, it can add resistance value(ohm)
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to set different resistance by identifying property
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"mediatek,rsel-resistance-in-si-unit".
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bias-pull-up:
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oneOf:
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- type: boolean
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- enum: [100, 101, 102, 103]
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description: mt8189 pull up PUPD/R0/R1 type define value.
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- enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
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description: mt8189 pull up RSEL type si unit value(ohm).
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description: |
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For pull up type is normal, it don't need add R1R0 define
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and resistance value.
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For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
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set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
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"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
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"MTK_PUPD_SET_R1R0_11" define in mt8189.
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For pull up type is PU/RSEL, it can add resistance value(ohm)
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to set different resistance by identifying property
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"mediatek,rsel-resistance-in-si-unit".
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bias-disable: true
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output-high: true
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output-low: true
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input-enable: true
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input-disable: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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required:
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- pinmux
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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- gpio-controller
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- '#gpio-cells'
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- gpio-ranges
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/pinctrl/mt65xx.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2)
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#define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2)
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8189-pinctrl";
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reg = <0x10005000 0x1000>,
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<0x11b50000 0x1000>,
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<0x11c50000 0x1000>,
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<0x11c60000 0x1000>,
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<0x11d20000 0x1000>,
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<0x11d30000 0x1000>,
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<0x11d40000 0x1000>,
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<0x11e20000 0x1000>,
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<0x11e30000 0x1000>,
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<0x11f20000 0x1000>,
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<0x11ce0000 0x1000>,
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<0x11de0000 0x1000>,
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<0x11e60000 0x1000>,
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<0x1c01e000 0x1000>,
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<0x11f00000 0x1000>;
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reg-names = "base", "lm", "rb0", "rb1", "bm0" , "bm1",
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"bm2", "lt0", "lt1", "rt", "eint0", "eint1",
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"eint2", "eint3", "eint4";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 182>;
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interrupt-controller;
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interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
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#interrupt-cells = <2>;
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i2c0-pins {
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pins {
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pinmux = <PINMUX_GPIO51__FUNC_SCL0>,
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<PINMUX_GPIO52__FUNC_SDA0>;
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bias-disable;
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};
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};
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};
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