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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9f77d234c1
Add a compatible for the exynos990-usbdrd-phy. The PHY is compatible with the older exynos5420 design (two clocks) when running in highspeed mode. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20250515-usb-resends-may-15-v3-1-ad33a85b6cee@mentallysanemainliners.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
254 lines
5.8 KiB
YAML
254 lines
5.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Marek Szyprowski <m.szyprowski@samsung.com>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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description: |
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For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
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compatible PHYs, the second cell in the PHY specifier identifies the
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PHY id, which is interpreted as follows::
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0 - UTMI+ type phy,
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1 - PIPE3 type phy.
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For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
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'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
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form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
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properties:
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compatible:
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enum:
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- google,gs101-usb31drd-phy
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- samsung,exynos2200-usb32drd-phy
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- samsung,exynos5250-usbdrd-phy
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- samsung,exynos5420-usbdrd-phy
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- samsung,exynos5433-usbdrd-phy
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- samsung,exynos7-usbdrd-phy
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- samsung,exynos7870-usbdrd-phy
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- samsung,exynos850-usbdrd-phy
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- samsung,exynos990-usbdrd-phy
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clocks:
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minItems: 1
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maxItems: 5
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clock-names:
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minItems: 1
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maxItems: 5
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description: |
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Typically two clocks:
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- Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
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for register access.
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- PHY reference clock (usually crystal clock), used for PHY operations,
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associated by phy name. It is used to determine bit values for clock
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settings register. For Exynos5420 this is given as 'sclk_usbphy30'
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in the CMU. It's not needed for Exynos2200.
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"#phy-cells":
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const: 1
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phys:
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maxItems: 1
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description:
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USBDRD-underlying high-speed PHY
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phy-names:
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const: hs
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Any connector to the data bus of this controller should be modelled using
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the OF graph bindings specified.
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reg:
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minItems: 1
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maxItems: 3
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reg-names:
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minItems: 1
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items:
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- const: phy
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- const: pcs
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- const: pma
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samsung,pmu-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to PMU system controller interface.
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vbus-supply:
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description:
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VBUS power source.
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vbus-boost-supply:
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description:
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VBUS Boost 5V power source.
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pll-supply:
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description: Power supply for the USB PLL.
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dvdd-usb20-supply:
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description: DVDD power supply for the USB 2.0 phy.
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vddh-usb20-supply:
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description: VDDh power supply for the USB 2.0 phy.
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vdd33-usb20-supply:
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description: 3.3V power supply for the USB 2.0 phy.
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vdda-usbdp-supply:
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description: VDDa power supply for the USB DP phy.
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vddh-usbdp-supply:
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description: VDDh power supply for the USB DP phy.
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required:
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- compatible
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- clocks
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- clock-names
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- "#phy-cells"
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- reg
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- samsung,pmu-syscon
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: google,gs101-usb31drd-phy
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then:
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$ref: /schemas/usb/usb-switch.yaml#
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properties:
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clocks:
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items:
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- description: Gate of main PHY clock
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- description: Gate of PHY reference clock
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- description: Gate of control interface AXI clock
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- description: Gate of control interface APB clock
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- description: Gate of SCL APB clock
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clock-names:
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items:
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- const: phy
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- const: ref
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- const: ctrl_aclk
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- const: ctrl_pclk
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- const: scl_pclk
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reg:
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minItems: 3
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reg-names:
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minItems: 3
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required:
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- reg-names
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- orientation-switch
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- port
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- pll-supply
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- dvdd-usb20-supply
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- vddh-usb20-supply
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- vdd33-usb20-supply
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- vdda-usbdp-supply
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- vddh-usbdp-supply
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos2200-usb32drd-phy
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: phy
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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required:
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- phys
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- phy-names
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos5433-usbdrd-phy
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- samsung,exynos7-usbdrd-phy
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: phy
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- const: ref
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- const: phy_utmi
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- const: phy_pipe
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- const: itp
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos5250-usbdrd-phy
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- samsung,exynos5420-usbdrd-phy
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- samsung,exynos7870-usbdrd-phy
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- samsung,exynos850-usbdrd-phy
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- samsung,exynos990-usbdrd-phy
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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items:
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- const: phy
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- const: ref
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5420.h>
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phy@12100000 {
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compatible = "samsung,exynos5420-usbdrd-phy";
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reg = <0x12100000 0x100>;
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#phy-cells = <1>;
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clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
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clock-names = "phy", "ref";
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samsung,pmu-syscon = <&pmu_system_controller>;
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vbus-supply = <&usb300_vbus_reg>;
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};
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