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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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301587cf4e
Add dt-binding schema for the MIPI C-/D-PHY found on Rockchip RK3588 SoCs. Tested-by: Daniel Semkowicz <dse@thaumatec.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Link: https://lore.kernel.org/r/20250313134035.278133-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
88 lines
1.9 KiB
YAML
88 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip MIPI D-/C-PHY with Samsung IP block
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maintainers:
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- Guochun Huang <hero.huang@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,rk3576-mipi-dcphy
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- rockchip,rk3588-mipi-dcphy
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reg:
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maxItems: 1
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"#phy-cells":
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const: 1
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description: |
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Argument is mode to operate in. Supported modes are:
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- PHY_TYPE_DPHY
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- PHY_TYPE_CPHY
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See include/dt-bindings/phy/phy.h for constants.
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: pclk
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- const: ref
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resets:
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maxItems: 4
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reset-names:
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items:
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- const: m_phy
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- const: apb
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- const: grf
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- const: s_phy
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the 'mipi dcphy general register files'.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@feda0000 {
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compatible = "rockchip,rk3588-mipi-dcphy";
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reg = <0x0 0xfeda0000 0x0 0x10000>;
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clocks = <&cru PCLK_MIPI_DCPHY0>,
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<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
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clock-names = "pclk", "ref";
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resets = <&cru SRST_M_MIPI_DCPHY0>,
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<&cru SRST_P_MIPI_DCPHY0>,
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<&cru SRST_P_MIPI_DCPHY0_GRF>,
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<&cru SRST_S_MIPI_DCPHY0>;
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reset-names = "m_phy", "apb", "grf", "s_phy";
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rockchip,grf = <&mipidcphy0_grf>;
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#phy-cells = <1>;
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};
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};
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