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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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ad205ffc0d
Add compatible for the HDPTX PHY on rk3576, which is compatible with rk3588, but without rst_phy/rst_ropll/rst_lcpll. In fact, these three reset lines are also optional on the rk3588, they just used for debug, then they were removed on the rk3576 IC design. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241231092721.252405-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
121 lines
2.6 KiB
YAML
121 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/rockchip,rk3588-hdptx-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip SoC HDMI/eDP Transmitter Combo PHY
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maintainers:
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- Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- rockchip,rk3588-hdptx-phy
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- items:
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- enum:
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- rockchip,rk3576-hdptx-phy
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- const: rockchip,rk3588-hdptx-phy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Reference clock
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- description: APB clock
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clock-names:
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items:
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- const: ref
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- const: apb
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"#clock-cells":
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const: 0
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"#phy-cells":
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const: 0
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resets:
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minItems: 4
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maxItems: 7
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reset-names:
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minItems: 4
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maxItems: 7
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Some PHY related data is accessed through GRF regs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- "#phy-cells"
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- resets
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- reset-names
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- rockchip,grf
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,rk3576-hdptx-phy
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then:
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properties:
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resets:
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minItems: 4
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maxItems: 4
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reset-names:
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items:
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- const: apb
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- const: init
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- const: cmn
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- const: lane
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else:
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properties:
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resets:
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minItems: 7
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maxItems: 7
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reset-names:
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items:
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- const: phy
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- const: apb
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- const: init
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- const: cmn
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- const: lane
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- const: ropll
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- const: lcpll
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@fed60000 {
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compatible = "rockchip,rk3588-hdptx-phy";
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reg = <0x0 0xfed60000 0x0 0x2000>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
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clock-names = "ref", "apb";
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#phy-cells = <0>;
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resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
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<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
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<&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
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<&cru SRST_HDPTX0_LCPLL>;
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reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
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rockchip,grf = <&hdptxphy_grf>;
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};
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};
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