mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-28 18:10:32 +00:00

Convert the Marvell CP110 combo PHY binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250607212605.743176-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
155 lines
3.2 KiB
YAML
155 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/phy/marvell,comphy-cp110.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Marvell MVEBU COMPHY Controller
|
|
|
|
maintainers:
|
|
- Miquel Raynal <miquel.raynal@bootlin.com>
|
|
|
|
description: >
|
|
COMPHY controllers can be found on the following Marvell MVEBU SoCs:
|
|
|
|
* Armada 7k/8k (on the CP110)
|
|
* Armada 3700
|
|
|
|
It provides a number of shared PHYs used by various interfaces (network, SATA,
|
|
USB, PCIe...).
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- marvell,comphy-cp110
|
|
- marvell,comphy-a3700
|
|
|
|
reg:
|
|
minItems: 1
|
|
items:
|
|
- description: Generic COMPHY registers
|
|
- description: Lane 1 (PCIe/GbE) registers (Armada 3700)
|
|
- description: Lane 0 (USB3/GbE) registers (Armada 3700)
|
|
- description: Lane 2 (SATA/USB3) registers (Armada 3700)
|
|
|
|
reg-names:
|
|
minItems: 1
|
|
items:
|
|
- const: comphy
|
|
- const: lane1_pcie_gbe
|
|
- const: lane0_usb3_gbe
|
|
- const: lane2_sata_usb3
|
|
|
|
'#address-cells':
|
|
const: 1
|
|
|
|
'#size-cells':
|
|
const: 0
|
|
|
|
clocks:
|
|
maxItems: 3
|
|
description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock
|
|
|
|
clock-names:
|
|
items:
|
|
- const: mg_clk
|
|
- const: mg_core_clk
|
|
- const: axi_clk
|
|
|
|
marvell,system-controller:
|
|
description: Phandle to the Marvell system controller (CP110 only)
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
|
|
|
patternProperties:
|
|
'^phy@[0-2]$':
|
|
description: A COMPHY lane child node
|
|
type: object
|
|
additionalProperties: false
|
|
|
|
properties:
|
|
reg:
|
|
description: COMPHY lane number
|
|
|
|
'#phy-cells':
|
|
const: 1
|
|
|
|
required:
|
|
- reg
|
|
- '#phy-cells'
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
|
|
additionalProperties: false
|
|
|
|
allOf:
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
const: marvell,comphy-a3700
|
|
|
|
then:
|
|
properties:
|
|
clocks: false
|
|
clock-names: false
|
|
|
|
required:
|
|
- reg-names
|
|
|
|
else:
|
|
required:
|
|
- marvell,system-controller
|
|
|
|
examples:
|
|
- |
|
|
phy@120000 {
|
|
compatible = "marvell,comphy-cp110";
|
|
reg = <0x120000 0x6000>;
|
|
clocks = <&clk 1 5>, <&clk 1 6>, <&clk 1 18>;
|
|
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
marvell,system-controller = <&syscon0>;
|
|
|
|
phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|
|
|
|
- |
|
|
phy@18300 {
|
|
compatible = "marvell,comphy-a3700";
|
|
reg = <0x18300 0x300>,
|
|
<0x1F000 0x400>,
|
|
<0x5C000 0x400>,
|
|
<0xe0178 0x8>;
|
|
reg-names = "comphy",
|
|
"lane1_pcie_gbe",
|
|
"lane0_usb3_gbe",
|
|
"lane2_sata_usb3";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
comphy0: phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
comphy1: phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
comphy2: phy@2 {
|
|
reg = <2>;
|
|
#phy-cells = <1>;
|
|
};
|
|
};
|