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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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5854d0aa52
Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581 PCIe-PHY binding. This change is not introducing any backward compatibility issue since the EN7581 dts is not upstream yet. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
70 lines
1.7 KiB
YAML
70 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Airoha EN7581 PCI-Express PHY
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maintainers:
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- Lorenzo Bianconi <lorenzo@kernel.org>
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description:
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The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
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properties:
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compatible:
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const: airoha,en7581-pcie-phy
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reg:
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items:
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- description: PCIE analog base address
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- description: PCIE lane0 base address
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- description: PCIE lane1 base address
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- description: PCIE lane0 detection time base address
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- description: PCIE lane1 detection time base address
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- description: PCIE Rx AEQ base address
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reg-names:
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items:
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- const: csr-2l
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- const: pma0
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- const: pma1
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- const: p0-xr-dtime
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- const: p1-xr-dtime
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- const: rx-aeq
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- reg-names
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@11e80000 {
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compatible = "airoha,en7581-pcie-phy";
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#phy-cells = <0>;
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reg = <0x0 0x1fa5a000 0x0 0xfff>,
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<0x0 0x1fa5b000 0x0 0xfff>,
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<0x0 0x1fa5c000 0x0 0xfff>,
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<0x0 0x1fc10044 0x0 0x4>,
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<0x0 0x1fc30044 0x0 0x4>,
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<0x0 0x1fc15030 0x0 0x104>;
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reg-names = "csr-2l", "pma0", "pma1",
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"p0-xr-dtime", "p1-xr-dtime",
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"rx-aeq";
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};
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};
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