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66461b43b0
Add device tree binding for StarFive's JH8100 StarLink PMU (Performance Monitor Unit). Signed-off-by: Ji Sheng Teoh <jisheng.teoh@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240229072720.3987876-3-jisheng.teoh@starfivetech.com Signed-off-by: Will Deacon <will@kernel.org>
47 lines
1.0 KiB
YAML
47 lines
1.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive JH8100 StarLink PMU
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maintainers:
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- Ji Sheng Teoh <jisheng.teoh@starfivetech.com>
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description:
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StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
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shared L3 memory system. The PMU support overflow interrupt, up to
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16 programmable 64bit event counters, and an independent 64bit cycle
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counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
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properties:
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compatible:
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const: starfive,jh8100-starlink-pmu
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pmu@12900000 {
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compatible = "starfive,jh8100-starlink-pmu";
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reg = <0x0 0x12900000 0x0 0x10000>;
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interrupts = <34>;
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};
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};
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