mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-04 18:49:41 +00:00
7255cfb199
Add a binding for implementations of the Arm CoreSight Performance Monitoring Unit Architecture. Not to be confused with CoreSight debug and trace, the PMU architecture defines a standard MMIO interface for event counters following a similar design to the CPU PMU architecture, where the implementation and most of its features are discoverable through ID registers. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/c62a86ef177bec5c6d12176c605de900e9e40c87.1706718007.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org>
40 lines
926 B
YAML
40 lines
926 B
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/perf/arm,coresight-pmu.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Arm Coresight Performance Monitoring Unit Architecture
|
|
|
|
maintainers:
|
|
- Robin Murphy <robin.murphy@arm.com>
|
|
|
|
properties:
|
|
compatible:
|
|
const: arm,coresight-pmu
|
|
|
|
reg:
|
|
items:
|
|
- description: Register page 0
|
|
- description: Register page 1, if the PMU implements the dual-page extension
|
|
minItems: 1
|
|
|
|
interrupts:
|
|
items:
|
|
- description: Overflow interrupt
|
|
|
|
cpus:
|
|
description: If the PMU is associated with a particular CPU or subset of CPUs,
|
|
array of phandles to the appropriate CPU node(s)
|
|
|
|
reg-io-width:
|
|
description: Granularity at which PMU register accesses are single-copy atomic
|
|
default: 4
|
|
enum: [4, 8]
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
|
|
additionalProperties: false
|