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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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9a5f8c7a81
Convert the v3,v360epc-pci binding to DT schema format. Add "clocks" which was not documented and is required. Drop "syscon" which was documented, but is not used. Drop the "v3,v360epc-pci" compatible by itself as this device is only used on the Arm Integrator/AP and not likely going to be used anywhere else at this point. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patch.msgid.link/20250505220139.2202164-1-robh@kernel.org
101 lines
3.5 KiB
YAML
101 lines
3.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/v3,v360epc-pci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: V3 Semiconductor V360 EPC PCI bridge
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description:
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This bridge is found in the ARM Integrator/AP (Application Platform)
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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items:
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- const: arm,integrator-ap-pci
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- const: v3,v360epc-pci
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reg:
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items:
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- description: V3 host bridge controller
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- description: Configuration space
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clocks:
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maxItems: 1
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dma-ranges:
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maxItems: 2
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description:
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The inbound ranges must be aligned to a 1MB boundary, and may be 1MB, 2MB,
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4MB, 8MB, 16MB, 32MB, 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The
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memory should be marked as pre-fetchable.
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interrupts:
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description: Bus Error IRQ
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maxItems: 1
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ranges:
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description:
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The non-prefetchable and prefetchable memory windows must each be exactly
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256MB (0x10000000) in size. The prefetchable memory window must be
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immediately adjacent to the non-prefetchable memory window.
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required:
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- compatible
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- reg
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- clocks
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- dma-ranges
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- "#interrupt-cells"
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- interrupt-map
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- interrupt-map-mask
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unevaluatedProperties: false
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examples:
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- |
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pci@62000000 {
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compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
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device_type = "pci";
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interrupt-parent = <&pic>;
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interrupts = <17>; /* Bus error IRQ */
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clocks = <&pciclk>;
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ranges = <0x01000000 0 0x00000000 0x60000000 0 0x01000000>, /* 16 MiB @ LB 60000000 */
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<0x02000000 0 0x40000000 0x40000000 0 0x10000000>, /* 256 MiB @ LB 40000000 1:1 */
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<0x42000000 0 0x50000000 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
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dma-ranges = <0x02000000 0 0x20000000 0x20000000 0 0x20000000>, /* EBI: 512 MB @ LB 20000000 1:1 */
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<0x02000000 0 0x80000000 0x80000000 0 0x40000000>; /* CM alias: 1GB @ LB 80000000 */
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map =
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/* IDSEL 9 */
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<0x4800 0 0 1 &pic 13>, /* INT A on slot 9 is irq 13 */
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<0x4800 0 0 2 &pic 14>, /* INT B on slot 9 is irq 14 */
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<0x4800 0 0 3 &pic 15>, /* INT C on slot 9 is irq 15 */
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<0x4800 0 0 4 &pic 16>, /* INT D on slot 9 is irq 16 */
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/* IDSEL 10 */
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<0x5000 0 0 1 &pic 14>, /* INT A on slot 10 is irq 14 */
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<0x5000 0 0 2 &pic 15>, /* INT B on slot 10 is irq 15 */
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<0x5000 0 0 3 &pic 16>, /* INT C on slot 10 is irq 16 */
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<0x5000 0 0 4 &pic 13>, /* INT D on slot 10 is irq 13 */
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/* IDSEL 11 */
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<0x5800 0 0 1 &pic 15>, /* INT A on slot 11 is irq 15 */
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<0x5800 0 0 2 &pic 16>, /* INT B on slot 11 is irq 16 */
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<0x5800 0 0 3 &pic 13>, /* INT C on slot 11 is irq 13 */
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<0x5800 0 0 4 &pic 14>, /* INT D on slot 11 is irq 14 */
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/* IDSEL 12 */
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<0x6000 0 0 1 &pic 16>, /* INT A on slot 12 is irq 16 */
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<0x6000 0 0 2 &pic 13>, /* INT B on slot 12 is irq 13 */
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<0x6000 0 0 3 &pic 14>, /* INT C on slot 12 is irq 14 */
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<0x6000 0 0 4 &pic 15>; /* INT D on slot 12 is irq 15 */
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};
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...
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