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cb08c3a32b
Add the "ti,syscon-acspcie-proxy-ctrl" device-tree property which is used to obtain a reference to the ACSPCIE Proxy Control register along with the details of the PAD IO Buffer output enable bits. The ACSPCIE Proxy Control register is used to drive the reference clock for the PCIe Endpoint device via the PAD IO Buffers of the ACSPCIE module. The ACSPCIE module can be used as an alternative to either an on-board clock generator or an external clock generator for providing the reference clock to the PCIe Endpoint device. Link: https://lore.kernel.org/linux-pci/20240829105316.1483684-2-s-vadapalli@ti.com Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
204 lines
4.7 KiB
YAML
204 lines
4.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI J721E PCI Host (PCIe Wrapper)
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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properties:
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compatible:
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oneOf:
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- const: ti,j721e-pcie-host
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- const: ti,j784s4-pcie-host
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- description: PCIe controller in AM64
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items:
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- const: ti,am64-pcie-host
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- const: ti,j721e-pcie-host
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- description: PCIe controller in J7200
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items:
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- const: ti,j7200-pcie-host
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- const: ti,j721e-pcie-host
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- description: PCIe controller in J722S
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items:
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- const: ti,j722s-pcie-host
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- const: ti,j721e-pcie-host
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: intd_cfg
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- const: user_cfg
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- const: reg
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- const: cfg
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ti,syscon-acspcie-proxy-ctrl:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to the ACSPCIE Proxy Control Register
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- description: Bitmask corresponding to the PAD IO Buffer
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output enable fields (Active Low).
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description: Specifier for enabling the ACSPCIE PAD outputs to drive
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the reference clock to the Endpoint device.
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ti,syscon-pcie-ctrl:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: Phandle to the SYSCON entry
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- description: pcie_ctrl register offset within SYSCON
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description: Specifier for configuring PCIe mode and link speed.
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power-domains:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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description: |+
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clock-specifier to represent input to the PCIe for 1 item.
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2nd item if present represents reference clock to the connector.
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clock-names:
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minItems: 1
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items:
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- const: fck
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- const: pcie_refclk
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dma-coherent: true
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vendor-id:
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const: 0x104c
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device-id:
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enum:
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- 0xb00d
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- 0xb00f
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- 0xb010
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- 0xb012
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- 0xb013
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msi-map: true
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: link_state
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interrupt-controller:
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type: object
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additionalProperties: false
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properties:
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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interrupts:
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maxItems: 1
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allOf:
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- $ref: cdns-pcie-host.yaml#
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- if:
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properties:
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compatible:
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enum:
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- ti,am64-pcie-host
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then:
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properties:
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num-lanes:
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const: 1
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- if:
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properties:
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compatible:
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enum:
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- ti,j7200-pcie-host
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- ti,j721e-pcie-host
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then:
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properties:
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num-lanes:
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minimum: 1
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maximum: 2
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- if:
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properties:
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compatible:
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enum:
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- ti,j784s4-pcie-host
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then:
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properties:
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num-lanes:
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minimum: 1
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maximum: 4
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required:
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- compatible
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- reg
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- reg-names
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- ti,syscon-pcie-ctrl
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- max-link-speed
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- num-lanes
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- power-domains
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- clocks
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- clock-names
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- vendor-id
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- device-id
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- msi-map
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- dma-ranges
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- ranges
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- reset-gpios
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- phys
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- phy-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include <dt-bindings/gpio/gpio.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie0_rc: pcie@2900000 {
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compatible = "ti,j721e-pcie-host";
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reg = <0x00 0x02900000 0x00 0x1000>,
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<0x00 0x02907000 0x00 0x400>,
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<0x00 0x0d000000 0x00 0x00800000>,
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<0x00 0x10000000 0x00 0x00001000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
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ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
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max-link-speed = <3>;
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num-lanes = <2>;
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power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 239 1>;
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clock-names = "fck";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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vendor-id = <0x104c>;
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device-id = <0xb00d>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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dma-coherent;
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reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
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<0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
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dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
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};
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};
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