mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-31 22:23:05 +00:00
27b1aac553
- Add qcom DT binding for 'global' interrupt (PCIe controller and link-specific events) for ipq8074, ipq8074-gen3, ipq6018, sa8775p, sc7280, sc8180x sdm845, sm8150, sm8250, sm8350 (Manivannan Sadhasivam) - Add qcom DT binding for 8 MSI SPI interrupts for msm8998, ipq8074, ipq8074-gen3, ipq6018 (Manivannan Sadhasivam) - Add dw rockchip DT binding for rk3576 and rk3562 (Kever Yang) - Correct indentation and style of examples in brcm,stb-pcie, cdns,cdns-pcie-ep, intel,keembay-pcie-ep, intel,keembay-pcie, microchip,pcie-host, rcar-pci-ep, rcar-pci-host, xilinx-versal-cpm (Krzysztof Kozlowski) - Fix include placement in sifive,fu740-pcie example (Krzysztof Kozlowski) - Convert Marvell EBU (dove, kirkwood, armada-370, armada-xp) and armada8k from text to schema DT bindings (Rob Herring) - Remove obsolete .txt DT bindings for content that has been moved to schemas (Rob Herring) - Add qcom DT binding for MHI registers in IPQ5332, IPQ6018, IPQ8074 and IPQ9574 (Varadarajan Narayanan) - Convert v3,v360epc-pci from text to DT schema binding (Rob Herring) - Change microchip,pcie-host DT binding to be 'dma-noncoherent' since PolarFire may be configured that way (Conor Dooley) * pci/dt-bindings: dt-bindings: PCI: microchip,pcie-host: Fix DMA coherency property dt-bindings: PCI: Convert v3,v360epc-pci to DT schema dt-bindings: PCI: qcom: Add MHI registers for IPQ9574 dt-bindings: PCI: Remove obsolete .txt docs dt-bindings: PCI: Convert marvell,armada8k-pcie to schema dt-bindings: PCI: Convert Marvell EBU to schema dt-bindings: PCI: sifive,fu740-pcie: Fix include placement in DTS example dt-bindings: PCI: Correct indentation and style in DTS example dt-bindings: PCI: dwc: rockchip: Add rk3562 support dt-bindings: PCI: dw: rockchip: Add rk3576 support dt-bindings: PCI: qcom,pcie-sc8180x: Add 'global' interrupt dt-bindings: PCI: qcom: Allow IPQ6018 to use 8 MSI and one 'global' interrupt dt-bindings: PCI: qcom: Allow IPQ8074 to use 8 MSI and one 'global' interrupt dt-bindings: PCI: qcom: Allow MSM8998 to use 8 MSI and one 'global' interrupt dt-bindings: PCI: qcom: Add 'global' interrupt for SDM845 SoC dt-bindings: PCI: qcom,pcie-sc7280: Add 'global' interrupt dt-bindings: PCI: qcom,pcie-sa8775p: Add 'global' interrupt dt-bindings: PCI: qcom,pcie-sm8350: Add 'global' interrupt dt-bindings: PCI: qcom,pcie-sm8250: Add 'global' interrupt dt-bindings: PCI: qcom,pcie-sm8150: Add 'global' interrupt
783 lines
21 KiB
YAML
783 lines
21 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm PCI express root complex
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description: |
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Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
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PCIe IP.
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properties:
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compatible:
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oneOf:
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- enum:
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- qcom,pcie-apq8064
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- qcom,pcie-apq8084
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- qcom,pcie-ipq4019
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- qcom,pcie-ipq5018
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064-v2
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- qcom,pcie-ipq8074
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-ipq9574
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- qcom,pcie-msm8996
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- qcom,pcie-qcs404
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- qcom,pcie-sdm845
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- qcom,pcie-sdx55
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- items:
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- enum:
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- qcom,pcie-ipq5332
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- qcom,pcie-ipq5424
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- const: qcom,pcie-ipq9574
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- items:
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- const: qcom,pcie-msm8998
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- const: qcom,pcie-msm8996
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reg:
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minItems: 4
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maxItems: 6
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reg-names:
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minItems: 4
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maxItems: 6
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interrupts:
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minItems: 1
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maxItems: 9
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interrupt-names:
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minItems: 1
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maxItems: 9
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iommu-map:
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minItems: 1
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maxItems: 16
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# Common definitions for clocks, clock-names and reset.
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# Platform constraints are described later.
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clocks:
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minItems: 3
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maxItems: 13
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clock-names:
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minItems: 3
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maxItems: 13
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dma-coherent: true
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: pcie-mem
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- const: cpu-pcie
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resets:
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minItems: 1
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maxItems: 12
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reset-names:
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minItems: 1
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maxItems: 12
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vdda-supply:
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description: A phandle to the core analog power supply
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vdda_phy-supply:
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description: A phandle to the core analog power supply for PHY
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vdda_refclk-supply:
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description: A phandle to the core analog power supply for IC which generates reference clock
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vddpe-3v3-supply:
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description: A phandle to the PCIe endpoint power supply
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pciephy
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power-domains:
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maxItems: 1
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perst-gpios:
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description: GPIO controlled connection to PERST# signal
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maxItems: 1
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required-opps:
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maxItems: 1
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wake-gpios:
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description: GPIO controlled connection to WAKE# signal
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupt-map-mask
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- interrupt-map
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- clocks
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- clock-names
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anyOf:
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- required:
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- interrupts
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- interrupt-names
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- "#interrupt-cells"
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- required:
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- msi-map
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8064
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- qcom,pcie-ipq4019
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064v2
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- qcom,pcie-ipq8074
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- qcom,pcie-qcs404
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then:
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properties:
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reg:
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minItems: 4
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maxItems: 4
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reg-names:
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items:
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: parf # Qualcomm specific registers
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- const: config # PCIe configuration space
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq5018
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8074-gen3
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- qcom,pcie-ipq9574
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: parf # Qualcomm specific registers
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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- qcom,pcie-msm8996
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- qcom,pcie-sdm845
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then:
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properties:
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reg:
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minItems: 4
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maxItems: 5
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reg-names:
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minItems: 4
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-sdx55
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then:
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properties:
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reg:
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minItems: 5
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maxItems: 6
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reg-names:
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minItems: 5
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items:
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- const: parf # Qualcomm specific registers
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- const: dbi # DesignWare PCIe registers
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- const: elbi # External local bus interface registers
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- const: atu # ATU address space
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- const: config # PCIe configuration space
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- const: mhi # MHI registers
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8064
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- qcom,pcie-ipq8064
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- qcom,pcie-ipq8064v2
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 5
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clock-names:
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minItems: 3
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items:
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- const: core # Clocks the pcie hw block
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- const: iface # Configuration AHB clock
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- const: phy # Clocks the pcie PHY block
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- const: aux # Clocks the pcie AUX block, not on apq8064
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- const: ref # Clocks the pcie ref block, not on apq8064
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resets:
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minItems: 5
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maxItems: 6
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reset-names:
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minItems: 5
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items:
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- const: axi # AXI reset
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- const: ahb # AHB reset
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- const: por # POR reset
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- const: pci # PCI reset
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- const: phy # PHY reset
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- const: ext # EXT reset, not on apq8064
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required:
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- vdda-supply
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- vdda_phy-supply
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- vdda_refclk-supply
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-apq8084
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: iface # Configuration AHB clock
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- const: master_bus # Master AXI clock
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- const: slave_bus # Slave AXI clock
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- const: aux # Auxiliary (AUX) clock
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: core # Core reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq4019
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: aux # Auxiliary (AUX) clock
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- const: master_bus # Master AXI clock
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- const: slave_bus # Slave AXI clock
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resets:
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minItems: 12
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maxItems: 12
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reset-names:
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items:
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- const: axi_m # AXI master reset
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- const: axi_s # AXI slave reset
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- const: pipe # PIPE reset
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- const: axi_m_vmid # VMID reset
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- const: axi_s_xpu # XPU reset
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- const: parf # PARF reset
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- const: phy # PHY reset
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- const: axi_m_sticky # AXI sticky reset
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- const: pipe_sticky # PIPE sticky reset
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- const: pwr # PWR reset
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- const: ahb # AHB reset
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- const: phy_ahb # PHY AHB reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq5018
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: ahb # AHB clock
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- const: aux # Auxiliary clock
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- const: axi_bridge # AXI bridge clock
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resets:
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minItems: 8
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maxItems: 8
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sleep # Sleep reset
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- const: sticky # Core sticky reset
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- const: axi_m # AXI master reset
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- const: axi_s # AXI slave reset
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- const: ahb # AHB reset
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- const: axi_m_sticky # AXI master sticky reset
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- const: axi_s_sticky # AXI slave sticky reset
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interrupts:
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minItems: 9
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maxItems: 9
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-msm8996
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: pipe # Pipe Clock driving internal logic
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- const: aux # Auxiliary (AUX) clock
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- const: cfg # Configuration clock
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- const: bus_master # Master AXI clock
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- const: bus_slave # Slave AXI clock
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resets: false
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reset-names: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq8074
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: ahb # AHB clock
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- const: aux # Auxiliary clock
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resets:
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minItems: 7
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maxItems: 7
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sleep # Sleep reset
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- const: sticky # Core Sticky reset
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: ahb # AHB Reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq6018
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- qcom,pcie-ipq8074-gen3
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then:
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properties:
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clocks:
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minItems: 5
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maxItems: 5
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: axi_bridge # AXI bridge clock
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- const: rchng
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resets:
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minItems: 8
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maxItems: 8
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sleep # Sleep reset
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- const: sticky # Core Sticky reset
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: ahb # AHB Reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: axi_s_sticky # AXI Slave Sticky reset
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-ipq9574
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then:
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properties:
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clocks:
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minItems: 6
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maxItems: 6
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clock-names:
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items:
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: axi_bridge
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- const: rchng
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- const: ahb
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- const: aux
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resets:
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minItems: 8
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maxItems: 8
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reset-names:
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items:
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- const: pipe # PIPE reset
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- const: sticky # Core Sticky reset
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- const: axi_s_sticky # AXI Slave Sticky reset
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- const: axi_s # AXI Slave reset
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- const: axi_m_sticky # AXI Master Sticky reset
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- const: axi_m # AXI Master reset
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- const: aux # AUX Reset
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- const: ahb # AHB Reset
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interrupts:
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minItems: 8
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interrupt-names:
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minItems: 8
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,pcie-qcs404
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then:
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properties:
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clocks:
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minItems: 4
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maxItems: 4
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clock-names:
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items:
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- const: iface # AHB clock
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- const: aux # Auxiliary clock
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- const: master_bus # AXI Master clock
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- const: slave_bus # AXI Slave clock
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resets:
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minItems: 6
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maxItems: 6
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reset-names:
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items:
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- const: axi_m # AXI Master reset
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- const: axi_s # AXI Slave reset
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- const: axi_m_sticky # AXI Master Sticky reset
|
|
- const: pipe_sticky # PIPE sticky reset
|
|
- const: pwr # PWR reset
|
|
- const: ahb # AHB reset
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- qcom,pcie-sdm845
|
|
then:
|
|
oneOf:
|
|
# Unfortunately the "optional" ref clock is used in the middle of the list
|
|
- properties:
|
|
clocks:
|
|
minItems: 8
|
|
maxItems: 8
|
|
clock-names:
|
|
items:
|
|
- const: pipe # PIPE clock
|
|
- const: aux # Auxiliary clock
|
|
- const: cfg # Configuration clock
|
|
- const: bus_master # Master AXI clock
|
|
- const: bus_slave # Slave AXI clock
|
|
- const: slave_q2a # Slave Q2A clock
|
|
- const: ref # REFERENCE clock
|
|
- const: tbu # PCIe TBU clock
|
|
- properties:
|
|
clocks:
|
|
minItems: 7
|
|
maxItems: 7
|
|
clock-names:
|
|
items:
|
|
- const: pipe # PIPE clock
|
|
- const: aux # Auxiliary clock
|
|
- const: cfg # Configuration clock
|
|
- const: bus_master # Master AXI clock
|
|
- const: bus_slave # Slave AXI clock
|
|
- const: slave_q2a # Slave Q2A clock
|
|
- const: tbu # PCIe TBU clock
|
|
properties:
|
|
resets:
|
|
maxItems: 1
|
|
reset-names:
|
|
items:
|
|
- const: pci # PCIe core reset
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- qcom,pcie-sdx55
|
|
then:
|
|
properties:
|
|
clocks:
|
|
minItems: 7
|
|
maxItems: 7
|
|
clock-names:
|
|
items:
|
|
- const: pipe # PIPE clock
|
|
- const: aux # Auxiliary clock
|
|
- const: cfg # Configuration clock
|
|
- const: bus_master # Master AXI clock
|
|
- const: bus_slave # Slave AXI clock
|
|
- const: slave_q2a # Slave Q2A clock
|
|
- const: sleep # PCIe Sleep clock
|
|
resets:
|
|
maxItems: 1
|
|
reset-names:
|
|
items:
|
|
- const: pci # PCIe core reset
|
|
|
|
- if:
|
|
not:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- qcom,pcie-apq8064
|
|
- qcom,pcie-ipq4019
|
|
- qcom,pcie-ipq5018
|
|
- qcom,pcie-ipq8064
|
|
- qcom,pcie-ipq8064v2
|
|
- qcom,pcie-ipq8074
|
|
- qcom,pcie-ipq8074-gen3
|
|
- qcom,pcie-ipq9574
|
|
- qcom,pcie-qcs404
|
|
then:
|
|
required:
|
|
- power-domains
|
|
|
|
- if:
|
|
not:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- qcom,pcie-msm8996
|
|
then:
|
|
required:
|
|
- resets
|
|
- reset-names
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- qcom,pcie-ipq6018
|
|
- qcom,pcie-ipq8074
|
|
- qcom,pcie-ipq8074-gen3
|
|
- qcom,pcie-msm8996
|
|
- qcom,pcie-msm8998
|
|
- qcom,pcie-sdm845
|
|
then:
|
|
oneOf:
|
|
- properties:
|
|
interrupts:
|
|
maxItems: 1
|
|
interrupt-names:
|
|
items:
|
|
- const: msi
|
|
- properties:
|
|
interrupts:
|
|
minItems: 8
|
|
maxItems: 9
|
|
interrupt-names:
|
|
minItems: 8
|
|
items:
|
|
- const: msi0
|
|
- const: msi1
|
|
- const: msi2
|
|
- const: msi3
|
|
- const: msi4
|
|
- const: msi5
|
|
- const: msi6
|
|
- const: msi7
|
|
- const: global
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- qcom,pcie-apq8064
|
|
- qcom,pcie-apq8084
|
|
- qcom,pcie-ipq4019
|
|
- qcom,pcie-ipq8064
|
|
- qcom,pcie-ipq8064-v2
|
|
- qcom,pcie-qcs404
|
|
then:
|
|
properties:
|
|
interrupts:
|
|
maxItems: 1
|
|
interrupt-names:
|
|
items:
|
|
- const: msi
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
pcie@1b500000 {
|
|
compatible = "qcom,pcie-ipq8064";
|
|
reg = <0x1b500000 0x1000>,
|
|
<0x1b502000 0x80>,
|
|
<0x1b600000 0x100>,
|
|
<0x0ff00000 0x100000>;
|
|
reg-names = "dbi", "elbi", "parf", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
|
|
<0x82000000 0 0 0x08000000 0 0x07e00000>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc 41>,
|
|
<&gcc 43>,
|
|
<&gcc 44>,
|
|
<&gcc 42>,
|
|
<&gcc 248>;
|
|
clock-names = "core", "iface", "phy", "aux", "ref";
|
|
resets = <&gcc 27>,
|
|
<&gcc 26>,
|
|
<&gcc 25>,
|
|
<&gcc 24>,
|
|
<&gcc 23>,
|
|
<&gcc 22>;
|
|
reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
|
|
pinctrl-0 = <&pcie_pins_default>;
|
|
pinctrl-names = "default";
|
|
vdda-supply = <&pm8921_s3>;
|
|
vdda_phy-supply = <&pm8921_lvs6>;
|
|
vdda_refclk-supply = <&ext_3p3v>;
|
|
};
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
pcie@fc520000 {
|
|
compatible = "qcom,pcie-apq8084";
|
|
reg = <0xfc520000 0x2000>,
|
|
<0xff000000 0x1000>,
|
|
<0xff001000 0x1000>,
|
|
<0xff002000 0x2000>;
|
|
reg-names = "parf", "dbi", "elbi", "config";
|
|
device_type = "pci";
|
|
linux,pci-domain = <0>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
|
|
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc 324>,
|
|
<&gcc 325>,
|
|
<&gcc 327>,
|
|
<&gcc 323>;
|
|
clock-names = "iface", "master_bus", "slave_bus", "aux";
|
|
resets = <&gcc 81>;
|
|
reset-names = "core";
|
|
power-domains = <&gcc 1>;
|
|
vdda-supply = <&pma8084_l3>;
|
|
phys = <&pciephy0>;
|
|
phy-names = "pciephy";
|
|
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
|
|
pinctrl-0 = <&pcie0_pins_default>;
|
|
pinctrl-names = "default";
|
|
};
|
|
...
|