linux-loongson/Documentation/devicetree/bindings/pci/qcom,pcie-sa8775p.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8775p.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SA8775p PCI Express Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  Qualcomm SA8775p SoC PCIe root complex controller is based on the Synopsys
  DesignWare PCIe IP.

properties:
  compatible:
    oneOf:
      - const: qcom,pcie-sa8775p
      - items:
          - enum:
              - qcom,pcie-qcs8300
          - const: qcom,pcie-sa8775p

  reg:
    minItems: 6
    maxItems: 6

  reg-names:
    items:
      - const: parf # Qualcomm specific registers
      - const: dbi # DesignWare PCIe registers
      - const: elbi # External local bus interface registers
      - const: atu # ATU address space
      - const: config # PCIe configuration space
      - const: mhi # MHI registers

  clocks:
    minItems: 5
    maxItems: 5

  clock-names:
    items:
      - const: aux # Auxiliary clock
      - const: cfg # Configuration clock
      - const: bus_master # Master AXI clock
      - const: bus_slave # Slave AXI clock
      - const: slave_q2a # Slave Q2A clock

  interrupts:
    minItems: 8
    maxItems: 9

  interrupt-names:
    minItems: 8
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7
      - const: global

  resets:
    items:
      - description: PCIe controller reset
      - description: PCIe link down reset

  reset-names:
    items:
      - const: pci
      - const: link_down

required:
  - interconnects
  - interconnect-names

allOf:
  - $ref: qcom,pcie-common.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie@1c00000 {
            compatible = "qcom,pcie-sa8775p";
            reg = <0x0 0x01c00000 0x0 0x3000>,
                  <0x0 0x40000000 0x0 0xf20>,
                  <0x0 0x40000f20 0x0 0xa8>,
                  <0x0 0x40001000 0x0 0x4000>,
                  <0x0 0x40100000 0x0 0x100000>,
                  <0x0 0x01c03000 0x0 0x1000>;
            reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;

            bus-range = <0x00 0xff>;
            device_type = "pci";
            linux,pci-domain = <0>;
            num-lanes = <2>;

            #address-cells = <3>;
            #size-cells = <2>;

            assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
            assigned-clock-rates = <19200000>;

            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
            clock-names = "aux",
                          "cfg",
                          "bus_master",
                          "bus_slave",
                          "slave_q2a";

            dma-coherent;

            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0",
                              "msi1",
                              "msi2",
                              "msi3",
                              "msi4",
                              "msi5",
                              "msi6",
                              "msi7",
                              "global";
            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
                            <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
                            <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
                            <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;

            interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
                            <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
            interconnect-names = "pcie-mem", "cpu-pcie";

            iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
                        <0x100 &pcie_smmu 0x0001 0x1>;

            phys = <&pcie0_phy>;
            phy-names = "pciephy";

            power-domains = <&gcc PCIE_0_GDSC>;

            resets = <&gcc GCC_PCIE_0_BCR>,
                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
            reset-names = "pci",
                          "link_down";

            perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
            wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
        };
    };