mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-28 18:10:32 +00:00
0c983d3544
Convert the Marvell EBU (Kirkwood, Dove, Armada XP/370) to DT schema format. Add "error" to interrupt-names which is in use, but missing. Shorten the example from 10 child nodes to 6 as the additional ones don't add much value to the example. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250414214157.1680484-1-robh@kernel.org
278 lines
10 KiB
YAML
278 lines
10 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/marvell,kirkwood-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell EBU PCIe interfaces
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maintainers:
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- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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- Pali Rohár <pali@kernel.org>
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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enum:
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- marvell,armada-370-pcie
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- marvell,armada-xp-pcie
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- marvell,dove-pcie
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- marvell,kirkwood-pcie
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ranges:
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description: >
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The ranges describing the MMIO registers have the following layout:
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0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
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where:
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* r is a 32-bits value that gives the offset of the MMIO registers of
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this PCIe interface, from the base of the internal registers.
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* s is a 32-bits value that give the size of this MMIO registers area.
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This range entry translates the '0x82000000 0 r' PCI address into the
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'MBUS_ID(0xf0, 0x01) r' CPU address, which is part of the internal
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register window (as identified by MBUS_ID(0xf0, 0x01)).
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The ranges describing the MBus windows have the following layout:
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0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
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where:
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* t is the type of the MBus window (as defined by the standard PCI DT
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bindings), 1 for I/O and 2 for memory.
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* s is the PCI slot that corresponds to this PCIe interface
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* w is the 'target ID' value for the MBus window
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* a the 'attribute' value for the MBus window.
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Since the location and size of the different MBus windows is not fixed in
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hardware, and only determined in runtime, those ranges cover the full first
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4 GB of the physical address space, and do not translate into a valid CPU
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address.
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msi-parent:
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maxItems: 1
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patternProperties:
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'^pcie@':
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type: object
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allOf:
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- $ref: /schemas/pci/pci-bus-common.yaml#
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- $ref: /schemas/pci/pci-device.yaml#
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unevaluatedProperties: false
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properties:
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clocks:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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interrupt-names:
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minItems: 1
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items:
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- const: intx
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- const: error
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reset-delay-us:
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default: 100000
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description: todo
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marvell,pcie-port:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 3
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description: todo
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marvell,pcie-lane:
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 3
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description: todo
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interrupt-controller:
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type: object
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additionalProperties: false
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properties:
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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required:
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- assigned-addresses
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- clocks
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- interrupt-map
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- marvell,pcie-port
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unevaluatedProperties: false
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examples:
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- |
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@f001000000000000 {
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compatible = "marvell,armada-xp-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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msi-parent = <&mpic>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
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0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
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0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
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0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
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0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
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0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
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0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
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0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
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0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
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0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
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0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
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0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
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0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
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0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
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0x81000000 0 0 0x81000000 0x1 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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num-lanes = <1>;
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/* low-active PERST# reset on GPIO 25 */
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reset-gpios = <&gpio0 25 1>;
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/* wait 20ms for device settle after reset deassertion */
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reset-delay-us = <20000>;
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clocks = <&gateclk 5>;
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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num-lanes = <1>;
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clocks = <&gateclk 6>;
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};
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
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0x81000000 0 0 0x81000000 0x3 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
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num-lanes = <1>;
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clocks = <&gateclk 7>;
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};
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
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0x81000000 0 0 0x81000000 0x4 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
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num-lanes = <1>;
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clocks = <&gateclk 8>;
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};
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pcie@5,0 {
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device_type = "pci";
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assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
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reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
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0x81000000 0 0 0x81000000 0x5 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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num-lanes = <1>;
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clocks = <&gateclk 9>;
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};
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pcie@6,0 {
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device_type = "pci";
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assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
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reg = <0x3000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
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0x81000000 0 0 0x81000000 0x6 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 63>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <1>;
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num-lanes = <1>;
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clocks = <&gateclk 10>;
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};
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};
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};
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...
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