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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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096d05bf3e
Convert the marvell,armada8k-pcie binding to DT schema. The binding uses different names for reg, clocks, and phys which have to be added to the common Synopsys DWC binding. The "marvell,reset-gpio" property was not documented. Mark it deprecated as the "reset-gpios" property can be used instead. The "msi-parent" property was also not documented. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://patch.msgid.link/20250414214135.1680076-1-robh@kernel.org
101 lines
2.0 KiB
YAML
101 lines
2.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/marvell,armada8k-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 7K/8K PCIe interface
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maintainers:
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- Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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description:
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
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select:
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properties:
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compatible:
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contains:
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enum:
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- marvell,armada8k-pcie
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required:
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- compatible
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allOf:
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- $ref: snps,dw-pcie.yaml#
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properties:
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compatible:
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items:
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- enum:
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- marvell,armada8k-pcie
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- const: snps,dw-pcie
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: ctrl
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- const: config
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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items:
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- const: core
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- const: reg
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interrupts:
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maxItems: 1
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msi-parent:
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maxItems: 1
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phys:
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minItems: 1
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maxItems: 4
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phy-names:
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minItems: 1
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maxItems: 4
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marvell,reset-gpio:
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maxItems: 1
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deprecated: true
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required:
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- interrupt-map
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- clocks
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- msi-parent
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie@f2600000 {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0xf2600000 0x10000>, <0xf6f00000 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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ranges = <0x81000000 0 0xf9000000 0xf9000000 0 0x10000>, /* downstream I/O */
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<0x82000000 0 0xf6000000 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clocks = <&cpm_syscon0 1 13>;
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};
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...
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