mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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5c2796adb1
Convert the Axis ARTPEC-6/7 PCIe binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250710180741.2970148-1-robh@kernel.org
119 lines
2.7 KiB
YAML
119 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2025 Axis AB
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/axis,artpec6-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Axis ARTPEC-6 PCIe host controller
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maintainers:
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- Jesper Nilsson <jesper.nilsson@axis.com>
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description:
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP.
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select:
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properties:
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compatible:
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contains:
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enum:
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- axis,artpec6-pcie
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- axis,artpec6-pcie-ep
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- axis,artpec7-pcie
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- axis,artpec7-pcie-ep
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required:
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- compatible
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properties:
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compatible:
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items:
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- enum:
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- axis,artpec6-pcie
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- axis,artpec6-pcie-ep
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- axis,artpec7-pcie
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- axis,artpec7-pcie-ep
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- const: snps,dw-pcie
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reg:
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minItems: 3
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maxItems: 4
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reg-names:
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minItems: 3
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maxItems: 4
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interrupts:
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maxItems: 1
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interrupt-names:
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items:
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- const: msi
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axis,syscon-pcie:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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System controller phandle used to enable and control the Synopsys IP.
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- axis,syscon-pcie
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oneOf:
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- $ref: snps,dw-pcie.yaml#
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properties:
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: dbi
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- const: phy
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- const: config
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- $ref: snps,dw-pcie-ep.yaml#
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properties:
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reg:
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minItems: 4
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: phy
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- const: addr_space
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@f8050000 {
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compatible = "axis,artpec6-pcie", "snps,dw-pcie";
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device_type = "pci";
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reg = <0xf8050000 0x2000
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0xf8040000 0x1000
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0xc0000000 0x2000>;
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reg-names = "dbi", "phy", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,
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<0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
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num-lanes = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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axis,syscon-pcie = <&syscon>;
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};
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