linux-loongson/Documentation/devicetree/bindings/pci/apple,pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/apple,pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple PCIe host controller

maintainers:
  - Mark Kettenis <kettenis@openbsd.org>

description: |
  The Apple PCIe host controller is a PCIe host controller with
  multiple root ports present in Apple ARM SoC platforms, including
  various iPhone and iPad devices and the "Apple Silicon" Macs.
  The controller incorporates Synopsys DesigWare PCIe logic to
  implements its root ports.  But the ATU found on most DesignWare
  PCIe host bridges is absent.

  On systems derived from T602x, the PHY registers are in a region
  separate from the port registers. In that case, there is one PHY
  register range per port register range.

  All root ports share a single ECAM space, but separate GPIOs are
  used to take the PCI devices on those ports out of reset.  Therefore
  the standard "reset-gpios" and "max-link-speed" properties appear on
  the child nodes that represent the PCI bridges that correspond to
  the individual root ports.

  MSIs are handled by the PCIe controller and translated into regular
  interrupts.  A range of 32 MSIs is provided.  These 32 MSIs can be
  distributed over the root ports as the OS sees fit by programming
  the PCIe controller's port registers.  

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - apple,t8103-pcie
              - apple,t8112-pcie
              - apple,t6000-pcie
          - const: apple,pcie
      - const: apple,t6020-pcie

  reg:
    minItems: 3
    maxItems: 10

  reg-names:
    minItems: 3
    items:
      - const: config
      - const: rc
      - const: port0
      - const: port1
      - const: port2
      - const: port3
      - const: phy0
      - const: phy1
      - const: phy2
      - const: phy3

  ranges:
    minItems: 2
    maxItems: 2

  interrupts:
    description:
      Interrupt specifiers, one for each root port.
    minItems: 1
    maxItems: 4

  msi-parent: true

  msi-ranges:
    maxItems: 1

  iommu-map: true
  iommu-map-mask: true

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - reg-names
  - bus-range
  - interrupts
  - msi-controller
  - msi-parent
  - msi-ranges

unevaluatedProperties: false

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#
  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
  - if:
      properties:
        compatible:
          contains:
            const: apple,t8103-pcie
    then:
      properties:
        reg:
          maxItems: 5
        interrupts:
          maxItems: 3
  - if:
      properties:
        compatible:
          contains:
            const: apple,t6020-pcie
    then:
      properties:
        reg-names:
          minItems: 10

examples:
  - |
    #include <dt-bindings/interrupt-controller/apple-aic.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      pcie0: pcie@690000000 {
        compatible = "apple,t8103-pcie", "apple,pcie";
        device_type = "pci";

        reg = <0x6 0x90000000 0x0 0x1000000>,
              <0x6 0x80000000 0x0 0x100000>,
              <0x6 0x81000000 0x0 0x4000>,
              <0x6 0x82000000 0x0 0x4000>,
              <0x6 0x83000000 0x0 0x4000>;
        reg-names = "config", "rc", "port0", "port1", "port2";

        interrupt-parent = <&aic>;
        interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>,
                     <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>;

        msi-controller;
        msi-parent = <&pcie0>;
        msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>;

        iommu-map = <0x100 &dart0 1 1>,
                    <0x200 &dart1 1 1>,
                    <0x300 &dart2 1 1>;
        iommu-map-mask = <0xff00>;

        bus-range = <0 3>;
        #address-cells = <3>;
        #size-cells = <2>;
        ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>,
                 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>;

        power-domains = <&ps_apcie_gp>;
        pinctrl-0 = <&pcie_pins>;
        pinctrl-names = "default";

        pci@0,0 {
          device_type = "pci";
          reg = <0x0 0x0 0x0 0x0 0x0>;
          reset-gpios = <&pinctrl_ap 152 0>;

          #address-cells = <3>;
          #size-cells = <2>;
          ranges;
        };

        pci@1,0 {
          device_type = "pci";
          reg = <0x800 0x0 0x0 0x0 0x0>;
          reset-gpios = <&pinctrl_ap 153 0>;

          #address-cells = <3>;
          #size-cells = <2>;
          ranges;
        };

        pci@2,0 {
          device_type = "pci";
          reg = <0x1000 0x0 0x0 0x0 0x0>;
          reset-gpios = <&pinctrl_ap 33 0>;

          #address-cells = <3>;
          #size-cells = <2>;
          ranges;
        };
      };
    };