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c96c936a0e
Add AMD Versal2 MDB (Multimedia DMA Bridge) PCIe Root Port Bridge. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20250228093351.923615-3-thippeswamy.havalige@amd.com Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
122 lines
3.0 KiB
YAML
122 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller
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maintainers:
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- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: amd,versal2-mdb-host
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reg:
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items:
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- description: MDB System Level Control and Status Register (SLCR) Base
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- description: configuration region
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- description: data bus interface
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- description: address translation unit register
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reg-names:
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items:
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- const: slcr
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- const: config
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- const: dbi
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- const: atu
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ranges:
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maxItems: 2
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msi-map:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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interrupt-map:
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maxItems: 4
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"#interrupt-cells":
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const: 1
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interrupt-controller:
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description: identifies the node as an interrupt controller
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type: object
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additionalProperties: false
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properties:
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interrupt-controller: true
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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required:
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- interrupt-controller
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- "#address-cells"
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- "#interrupt-cells"
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required:
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- reg
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- reg-names
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- interrupts
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- interrupt-map
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- interrupt-map-mask
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- msi-map
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- "#interrupt-cells"
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- interrupt-controller
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@ed931000 {
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compatible = "amd,versal2-mdb-host";
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reg = <0x0 0xed931000 0x0 0x2000>,
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<0x1000 0x100000 0x0 0xff00000>,
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<0x1000 0x0 0x0 0x1000>,
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<0x0 0xed860000 0x0 0x2000>;
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reg-names = "slcr", "config", "dbi", "atu";
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ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>,
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<0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
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<0 0 0 2 &pcie_intc_0 1>,
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<0 0 0 3 &pcie_intc_0 2>,
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<0 0 0 4 &pcie_intc_0 3>;
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msi-map = <0x0 &gic_its 0x00 0x10000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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pcie_intc_0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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