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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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c1d9667108
Add "clocks" bindings for the input clock. Signed-off-by: Vineeth Karumanchi <vineeth.karumanchi@amd.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: David S. Miller <davem@davemloft.net>
61 lines
1.6 KiB
YAML
61 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx GMII to RGMII Converter
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maintainers:
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- Harini Katakam <harini.katakam@amd.com>
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description:
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The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
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Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
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ethernet physical media devices (PHY) and the Gigabit Ethernet controller.
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This core can be used in all three modes of operation(10/100/1000 Mb/s).
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The Management Data Input/Output (MDIO) interface is used to configure the
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speed of operation. This core can switch dynamically between the three
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different speed modes by configuring the converter register through mdio write.
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The core cannot function without an external phy connected to it.
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properties:
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compatible:
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const: xlnx,gmii-to-rgmii-1.0
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reg:
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minimum: 0
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maximum: 31
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description: The ID number for the phy.
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phy-handle:
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$ref: ethernet-controller.yaml#/properties/phy-handle
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clocks:
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items:
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- description: 200/375 MHz free-running clock is used as input clock.
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required:
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- compatible
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- reg
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- phy-handle
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unevaluatedProperties: false
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examples:
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@0 {
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reg = <0>;
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};
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gmiitorgmii@8 {
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compatible = "xlnx,gmii-to-rgmii-1.0";
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reg = <8>;
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phy-handle = <&phy>;
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clocks = <&dummy>;
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};
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};
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