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09277e4fc9
Per the RMII specification, the REF_CLK is sourced from MAC to PHY or from an external source. But for TJA11xx PHYs, they support to output a 50MHz RMII reference clock on REF_CLK pin. Previously the "nxp,rmii-refclk-in" was added to indicate that in RMII mode, if this property present, REF_CLK is input to the PHY, otherwise it is output. This seems inappropriate now. Because according to the RMII specification, the REF_CLK is originally input, so there is no need to add an additional "nxp,rmii-refclk-in" property to declare that REF_CLK is input. Unfortunately, because the "nxp,rmii-refclk-in" property has been added for a while, and we cannot confirm which DTS use the TJA1100 and TJA1101 PHYs, changing it to switch polarity will cause an ABI break. But fortunately, this property is only valid for TJA1100 and TJA1101. For TJA1103/TJA1104/TJA1120/TJA1121 PHYs, this property is invalid because they use the nxp-c45-tja11xx driver, which is a different driver from TJA1100/TJA1101. Therefore, for PHYs using nxp-c45-tja11xx driver, add "nxp,rmii-refclk-out" property to support outputting RMII reference clock on REF_CLK pin. Signed-off-by: Wei Fang <wei.fang@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
128 lines
3.5 KiB
YAML
128 lines
3.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0+
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP TJA11xx PHY
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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- Florian Fainelli <f.fainelli@gmail.com>
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- Heiner Kallweit <hkallweit1@gmail.com>
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description:
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Bindings for NXP TJA11xx automotive PHYs
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properties:
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compatible:
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enum:
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- ethernet-phy-id0180.dc40
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- ethernet-phy-id0180.dc41
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- ethernet-phy-id0180.dc48
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- ethernet-phy-id0180.dd00
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- ethernet-phy-id0180.dd01
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- ethernet-phy-id0180.dd02
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- ethernet-phy-id0180.dc80
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- ethernet-phy-id0180.dc82
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- ethernet-phy-id001b.b010
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- ethernet-phy-id001b.b013
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- ethernet-phy-id001b.b030
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- ethernet-phy-id001b.b031
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allOf:
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- $ref: ethernet-phy.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ethernet-phy-id0180.dc40
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- ethernet-phy-id0180.dc41
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- ethernet-phy-id0180.dc48
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- ethernet-phy-id0180.dd00
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- ethernet-phy-id0180.dd01
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- ethernet-phy-id0180.dd02
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then:
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properties:
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nxp,rmii-refclk-in:
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type: boolean
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description: |
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The REF_CLK is provided for both transmitted and received data
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in RMII mode. This clock signal is provided by the PHY and is
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typically derived from an external 25MHz crystal. Alternatively,
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a 50MHz clock signal generated by an external oscillator can be
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connected to pin REF_CLK. A third option is to connect a 25MHz
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clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
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as input or output according to the actual circuit connection.
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If present, indicates that the REF_CLK will be configured as
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interface reference clock input when RMII mode enabled.
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If not present, the REF_CLK will be configured as interface
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reference clock output when RMII mode enabled.
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Only supported on TJA1100 and TJA1101.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ethernet-phy-id001b.b010
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- ethernet-phy-id001b.b013
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- ethernet-phy-id001b.b030
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- ethernet-phy-id001b.b031
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then:
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properties:
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nxp,rmii-refclk-out:
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type: boolean
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description: Enable 50MHz RMII reference clock output on REF_CLK pin.
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patternProperties:
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"^ethernet-phy@[0-9a-f]+$":
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type: object
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additionalProperties: false
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description: |
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Some packages have multiple PHYs. Secondary PHY should be defines as
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subnode of the first (parent) PHY.
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properties:
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reg:
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minimum: 0
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maximum: 31
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description:
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The ID number for the child PHY. Should be +1 of parent PHY.
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required:
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- reg
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unevaluatedProperties: false
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examples:
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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tja1101_phy0: ethernet-phy@4 {
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compatible = "ethernet-phy-id0180.dc40";
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reg = <0x4>;
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nxp,rmii-refclk-in;
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};
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};
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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tja1102_phy0: ethernet-phy@4 {
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reg = <0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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tja1102_phy1: ethernet-phy@5 {
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reg = <0x5>;
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};
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};
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};
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