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The code has been updated to follow what datasheet says about the polarity of the reset pin, which is active-low. Update the device tree bindings accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/20250305105656.2133487-5-andriy.shevchenko@linux.intel.com Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
29 lines
933 B
Plaintext
29 lines
933 B
Plaintext
* CA8210 IEEE 802.15.4 *
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Required properties:
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- compatible: Should be "cascoda,ca8210"
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- reg: Controlling chip select
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- spi-max-frequency: Maximum clock speed, should be *less than*
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4000000
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- spi-cpol: Requires inverted clock polarity
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- reset-gpio: GPIO attached to reset
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- irq-gpio: GPIO attached to IRQ
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Optional properties:
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- extclock-enable: Include for the ca8210 to route its 16MHz clock
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to an output
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- extclock-freq: Frequency in Hz of the external clock
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- extclock-gpio: GPIO of the ca8210 to output the clock on
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Example:
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ca8210@0 {
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compatible = "cascoda,ca8210";
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reg = <0>;
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spi-max-frequency = <3000000>;
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spi-cpol;
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reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>;
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irq-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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extclock-enable;
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extclock-freq = 16000000;
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extclock-gpio = 2;
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};
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