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Add a binding for the "Gianfar" ethernet controller, also known as TSEC/eTSEC. Signed-off-by: J. Neuschäfer <j.ne@posteo.net> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250228-gianfar-yaml-v2-3-6beeefbd4818@posteo.net Signed-off-by: Jakub Kicinski <kuba@kernel.org>
249 lines
5.9 KiB
YAML
249 lines
5.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/fsl,gianfar.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Three-Speed Ethernet Controller (TSEC), "Gianfar"
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maintainers:
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- J. Neuschäfer <j.ne@posteo.net>
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# This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because
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# both use compatible = "gianfar" (with different device_type values)
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select:
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oneOf:
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- properties:
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compatible:
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contains:
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const: gianfar
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device_type:
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const: network
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required:
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- device_type
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- properties:
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compatible:
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const: fsl,etsec2
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required:
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- compatible
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properties:
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compatible:
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enum:
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- gianfar
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- fsl,etsec2
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device_type:
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const: network
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model:
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enum:
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- FEC
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- TSEC
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- eTSEC
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reg:
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maxItems: 1
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ranges: true
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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interrupts:
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minItems: 1
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items:
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- description: Transmit interrupt or single combined interrupt
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- description: Receive interrupt
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- description: Error interrupt
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dma-coherent: true
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fsl,magic-packet:
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type: boolean
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description:
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If present, indicates that the hardware supports waking up via magic packet.
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fsl,wake-on-filer:
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type: boolean
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description:
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If present, indicates that the hardware supports waking up by Filer
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General Purpose Interrupt (FGPI) asserted on the Rx int line. This is
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an advanced power management capability allowing certain packet types
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(user) defined by filer rules to wake up the system.
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bd-stash:
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type: boolean
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description:
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If present, indicates that the hardware supports stashing buffer
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descriptors in the L2.
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rx-stash-len:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Denotes the number of bytes of a received buffer to stash in the L2.
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rx-stash-idx:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Denotes the index of the first byte from the received buffer to stash in
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the L2.
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fsl,num_rx_queues:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of receive queues
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const: 8
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fsl,num_tx_queues:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of transmit queues
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const: 8
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tbi-handle:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Reference (phandle) to the TBI node
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required:
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- compatible
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- model
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patternProperties:
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"^mdio@[0-9a-f]+$":
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$ref: /schemas/net/fsl,gianfar-mdio.yaml#
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allOf:
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- $ref: ethernet-controller.yaml#
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# eTSEC2 controller nodes have "queue group" subnodes and don't need a "reg"
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# property.
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- if:
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properties:
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compatible:
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contains:
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const: fsl,etsec2
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then:
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patternProperties:
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"^queue-group@[0-9a-f]+$":
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type: object
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properties:
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Transmit interrupt
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- description: Receive interrupt
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- description: Error interrupt
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required:
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- reg
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- interrupts
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additionalProperties: false
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else:
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required:
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- reg
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# TSEC and eTSEC devices require three interrupts
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- if:
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properties:
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model:
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contains:
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enum: [ TSEC, eTSEC ]
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then:
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properties:
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interrupts:
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items:
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- description: Transmit interrupt
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- description: Receive interrupt
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- description: Error interrupt
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unevaluatedProperties: false
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examples:
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- |
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ethernet@24000 {
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2>, <30 2>, <34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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ethernet@24000 {
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 IRQ_TYPE_LEVEL_LOW>,
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<33 IRQ_TYPE_LEVEL_LOW>,
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<34 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&ipic>;
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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};
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};
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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ethernet {
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compatible = "fsl,etsec2";
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ranges;
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device_type = "network";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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model = "eTSEC";
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fsl,magic-packet;
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dma-coherent;
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queue-group@2d10000 {
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reg = <0x0 0x2d10000 0x0 0x1000>;
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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};
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queue-group@2d14000 {
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reg = <0x0 0x2d14000 0x0 0x1000>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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...
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