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a0f29a07b6
After studying the datasheets for some of the KS8995 variants it becomes pretty obvious that this is a straight-forward and simple MII DSA switch with one port in (CPU) and four outgoing ports, and it even supports custom tags by setting a bit in a special register, and elaborate VLAN handling as all DSA switches do. What is a bit odd with KS8995 is that it uses an extra MII-P5 port to access one of the PHYs separately, on the side of the switch fabric, such as when using a WAN port separately from a LAN switch in a home router. Rewrite the terse bindings to YAML, and move to the proper subdirectory. Include a verbose example to make things clear. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250625-ks8995-dsa-bindings-v2-1-ce71dce9be0b@linaro.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
136 lines
3.0 KiB
YAML
136 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/micrel,ks8995.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Micrel KS8995 Family DSA Switches
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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description:
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The Micrel KS8995 DSA Switches are 100 Mbit switches that were produced in
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the early-to-mid 2000s. The chip features a CPU port and four outgoing ports,
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each with an internal PHY. The chip itself is managed over SPI, but all the
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PHYs need to be accessed from an external MDIO channel.
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Further, a fifth PHY is available and can be used separately from the switch
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fabric, connected to an external MII interface name MII-P5. This is
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unrelated from the CPU-facing port 5 which is used for DSA MII traffic.
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properties:
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compatible:
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enum:
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- micrel,ks8995
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- micrel,ksz8795
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- micrel,ksz8864
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reg:
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maxItems: 1
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reset-gpios:
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description: GPIO to be used to reset the whole device
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maxItems: 1
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allOf:
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- $ref: dsa.yaml#/$defs/ethernet-ports
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@0 {
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compatible = "micrel,ks8995";
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reg = <0>;
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spi-max-frequency = <25000000>;
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-port@0 {
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reg = <0>;
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label = "lan1";
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};
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ethernet-port@1 {
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reg = <1>;
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label = "lan2";
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};
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ethernet-port@2 {
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reg = <2>;
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label = "lan3";
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};
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ethernet-port@3 {
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reg = <3>;
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label = "lan4";
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};
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ethernet-port@4 {
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reg = <4>;
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ethernet = <&mac2>;
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phy-mode = "mii";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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/* The WAN port connected on MII-P5 */
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ethernet-port@1000 {
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reg = <0x00001000 0x1000>;
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label = "wan";
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phy-mode = "mii";
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phy-handle = <&phy5>;
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};
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mac2: ethernet-port@2000 {
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reg = <0x00002000 0x1000>;
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phy-mode = "mii";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* LAN PHYs 1-4 accessible over external MDIO */
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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};
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/* WAN PHY accessible over external MDIO */
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phy5: ethernet-phy@5 {
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reg = <5>;
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};
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};
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