mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00
e0a4f50fce
Convert the bindings to yaml format. Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
125 lines
3.1 KiB
YAML
125 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/mtd/ti,davinci-nand.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: TI DaVinci NAND controller
|
|
|
|
maintainers:
|
|
- Marcus Folkesson <marcus.folkesson@gmail.com>
|
|
|
|
allOf:
|
|
- $ref: nand-controller.yaml
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- ti,davinci-nand
|
|
- ti,keystone-nand
|
|
|
|
reg:
|
|
items:
|
|
- description: Access window.
|
|
- description: AEMIF control registers.
|
|
|
|
partitions:
|
|
$ref: /schemas/mtd/partitions/partitions.yaml
|
|
|
|
ti,davinci-chipselect:
|
|
description:
|
|
Number of chipselect. Indicate on the davinci_nand driver which
|
|
chipselect is used for accessing the nand.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
enum: [0, 1, 2, 3]
|
|
|
|
ti,davinci-mask-ale:
|
|
description:
|
|
Mask for ALE. Needed for executing address phase. These offset will be
|
|
added to the base address for the chip select space the NAND Flash
|
|
device is connected to.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
default: 0x08
|
|
|
|
ti,davinci-mask-cle:
|
|
description:
|
|
Mask for CLE. Needed for executing command phase. These offset will be
|
|
added to the base address for the chip select space the NAND Flash device
|
|
is connected to.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
default: 0x10
|
|
|
|
ti,davinci-mask-chipsel:
|
|
description:
|
|
Mask for chipselect address. Needed to mask addresses for given
|
|
chipselect.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
default: 0
|
|
|
|
ti,davinci-ecc-bits:
|
|
description: Used ECC bits.
|
|
enum: [1, 4]
|
|
|
|
ti,davinci-ecc-mode:
|
|
description: Operation mode of the NAND ECC mode.
|
|
$ref: /schemas/types.yaml#/definitions/string
|
|
enum: [none, soft, hw, on-die]
|
|
deprecated: true
|
|
|
|
ti,davinci-nand-buswidth:
|
|
description: Bus width to the NAND chip.
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
enum: [8, 16]
|
|
default: 8
|
|
deprecated: true
|
|
|
|
ti,davinci-nand-use-bbt:
|
|
type: boolean
|
|
description:
|
|
Use flash based bad block table support. OOB identifier is saved in OOB
|
|
area.
|
|
deprecated: true
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- ti,davinci-chipselect
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
bus {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
|
|
nand-controller@2000000,0 {
|
|
compatible = "ti,davinci-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0 0x02000000 0x02000000>,
|
|
<1 0x00000000 0x00008000>;
|
|
|
|
ti,davinci-chipselect = <1>;
|
|
ti,davinci-mask-ale = <0>;
|
|
ti,davinci-mask-cle = <0>;
|
|
ti,davinci-mask-chipsel = <0>;
|
|
|
|
ti,davinci-nand-buswidth = <16>;
|
|
ti,davinci-ecc-mode = "hw";
|
|
ti,davinci-ecc-bits = <4>;
|
|
ti,davinci-nand-use-bbt;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot env";
|
|
reg = <0 0x020000>;
|
|
};
|
|
};
|
|
};
|
|
};
|