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c67ea7d22e
Add bindings for Xilinx ZynqMP OCM controller. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230104084512.1855243-2-sai.krishna.potthuri@amd.com
46 lines
1.2 KiB
YAML
46 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
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maintainers:
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- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
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- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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description: |
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The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
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and recover from a single-bit memory fault.On a write, if all bytes are
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being written, the ECC is generated and written into the ECC RAM along with
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the write-data that is written into the data RAM. If one or more bytes are
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not written, then the read operation results in an correctable error or
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uncorrectable error.
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properties:
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compatible:
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const: xlnx,zynqmp-ocmc-1.0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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memory-controller@ff960000 {
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compatible = "xlnx,zynqmp-ocmc-1.0";
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reg = <0xff960000 0x1000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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};
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