mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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0b226380d4
Add bindings for the Memory Controller (MC) and External Memory Controller (EMC) found on the Tegra264 SoC. Tegra264 SoC has a different number of interrupt lines for MC sub-units: UCF_SOC, hub, hub common, syncpoint and MC channel. The total number of interrupt lines is eight. Update maxItems for MC interrupts accordingly. This also adds a header containing the memory client ID definitions that are used by the interconnects property in DT and the tegra_mc_client table in the MC driver. These IDs are defined by the hardware, so the numbering doesn't start at 0 and contains holes. Also added are the stream IDs for various hardware blocks found on Tegra264. These are allocated as blocks of 256 IDs and each block can be subdivided for additional fine-grained isolation if needed. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> [treding@nvidia.com: add SMMU stream IDs, squash patches] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250709222147.3758356-2-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com>
357 lines
8.4 KiB
YAML
357 lines
8.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra186 (and later) SoC Memory Controller
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maintainers:
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- Jon Hunter <jonathanh@nvidia.com>
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- Thierry Reding <thierry.reding@gmail.com>
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description: |
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The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
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into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
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handles memory requests for 40-bit virtual addresses from internal clients
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and arbitrates among them to allocate memory bandwidth.
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Up to 15 GiB of physical memory can be supported. Security features such as
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encryption of traffic to and from DRAM via general security apertures are
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available for video and other secure applications, as well as DRAM ECC for
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automotive safety applications (single bit error correction and double bit
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error detection).
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properties:
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$nodename:
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pattern: "^memory-controller@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- nvidia,tegra186-mc
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- nvidia,tegra194-mc
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- nvidia,tegra234-mc
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- nvidia,tegra264-mc
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reg:
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minItems: 6
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maxItems: 18
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reg-names:
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minItems: 6
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maxItems: 18
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interrupts:
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minItems: 1
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maxItems: 8
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interrupt-names:
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minItems: 1
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maxItems: 8
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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ranges: true
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dma-ranges: true
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"#interconnect-cells":
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const: 1
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patternProperties:
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"^external-memory-controller@[0-9a-f]+$":
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description:
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The bulk of the work involved in controlling the external memory
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controller on NVIDIA Tegra186 and later is performed on the BPMP. This
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coprocessor exposes the EMC clock that is used to set the frequency at
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which the external memory is clocked and a remote procedure call that
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can be used to obtain the set of available frequencies.
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type: object
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properties:
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compatible:
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items:
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- enum:
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- nvidia,tegra186-emc
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- nvidia,tegra194-emc
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- nvidia,tegra234-emc
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- nvidia,tegra264-emc
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reg:
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minItems: 1
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maxItems: 2
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interrupts:
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items:
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- description: EMC general interrupt
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clocks:
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items:
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- description: external memory clock
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clock-names:
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items:
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- const: emc
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"#interconnect-cells":
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const: 0
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of the node representing the BPMP
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allOf:
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- if:
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properties:
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compatible:
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const: nvidia,tegra186-emc
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then:
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properties:
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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const: nvidia,tegra194-emc
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then:
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properties:
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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const: nvidia,tegra234-emc
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then:
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properties:
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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const: nvidia,tegra264-emc
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then:
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properties:
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reg:
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minItems: 2
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#interconnect-cells"
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- nvidia,bpmp
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allOf:
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- if:
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properties:
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compatible:
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const: nvidia,tegra186-mc
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then:
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properties:
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reg:
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maxItems: 6
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description: 5 memory controller channels and 1 for stream-id registers
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reg-names:
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items:
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- const: sid
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- const: broadcast
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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const: nvidia,tegra194-mc
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then:
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properties:
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reg:
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minItems: 18
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description: 17 memory controller channels and 1 for stream-id registers
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reg-names:
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items:
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- const: sid
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- const: broadcast
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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- const: ch4
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- const: ch5
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- const: ch6
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- const: ch7
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- const: ch8
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- const: ch9
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- const: ch10
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- const: ch11
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- const: ch12
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- const: ch13
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- const: ch14
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- const: ch15
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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const: nvidia,tegra234-mc
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then:
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properties:
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reg:
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minItems: 18
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description: 17 memory controller channels and 1 for stream-id registers
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reg-names:
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items:
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- const: sid
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- const: broadcast
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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- const: ch4
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- const: ch5
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- const: ch6
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- const: ch7
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- const: ch8
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- const: ch9
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- const: ch10
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- const: ch11
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- const: ch12
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- const: ch13
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- const: ch14
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- const: ch15
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interrupts:
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items:
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- description: MC general interrupt
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interrupt-names: false
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- if:
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properties:
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compatible:
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const: nvidia,tegra264-mc
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then:
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properties:
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reg:
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minItems: 17
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maxItems: 17
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description: 17 memory controller channels
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reg-names:
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items:
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- const: broadcast
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- const: ch0
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- const: ch1
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- const: ch2
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- const: ch3
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- const: ch4
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- const: ch5
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- const: ch6
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- const: ch7
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- const: ch8
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- const: ch9
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- const: ch10
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- const: ch11
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- const: ch12
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- const: ch13
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- const: ch14
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- const: ch15
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interrupts:
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minItems: 8
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maxItems: 8
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description: One interrupt line for each MC component
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interrupt-names:
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items:
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- const: mcf
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- const: hub1
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- const: hub2
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- const: hub3
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- const: hub4
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- const: hub5
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- const: sbs
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- const: channel
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additionalProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- "#address-cells"
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- "#size-cells"
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examples:
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- |
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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memory-controller@2c00000 {
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compatible = "nvidia,tegra186-mc";
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reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
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<0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */
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<0x0 0x02c20000 0x0 0x10000>, /* MC0 */
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<0x0 0x02c30000 0x0 0x10000>, /* MC1 */
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<0x0 0x02c40000 0x0 0x10000>, /* MC2 */
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<0x0 0x02c50000 0x0 0x10000>; /* MC3 */
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reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3";
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
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/*
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* Memory clients have access to all 40 bits that the memory
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* controller can address.
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*/
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dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
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external-memory-controller@2c60000 {
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compatible = "nvidia,tegra186-emc";
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reg = <0x0 0x02c60000 0x0 0x50000>;
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interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA186_CLK_EMC>;
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clock-names = "emc";
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#interconnect-cells = <0>;
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nvidia,bpmp = <&bpmp>;
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};
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};
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};
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