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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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2632f288ab
The VSPD block on the RZ/V2N SoC is identical to the one found on the RZ/G2L SoC. No driver changes are required, as `renesas,r9a07g044-vsp2` will be used as a fallback compatible string on the RZ/V2N SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20250530154148.374663-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
135 lines
3.1 KiB
YAML
135 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/renesas,vsp1.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas VSP Video Processing Engine
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maintainers:
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- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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description:
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The VSP is a video processing engine that supports up-/down-scaling, alpha
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blending, color space conversion and various other image processing features.
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It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
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properties:
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compatible:
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oneOf:
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- enum:
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- renesas,r9a07g044-vsp2 # RZ/G2L
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- renesas,vsp1 # R-Car Gen2 and RZ/G1
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- renesas,vsp2 # R-Car Gen3 and RZ/G2
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- items:
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- enum:
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- renesas,r9a07g043u-vsp2 # RZ/G2UL
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- renesas,r9a07g054-vsp2 # RZ/V2L
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- renesas,r9a09g056-vsp2 # RZ/V2N
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- renesas,r9a09g057-vsp2 # RZ/V2H(P)
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- const: renesas,r9a07g044-vsp2 # RZ/G2L fallback
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: Main clock
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- description: Register access clock
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- description: Video clock
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clock-names:
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items:
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- const: aclk
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- const: pclk
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- const: vclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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renesas,fcp:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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A phandle referencing the FCP that handles memory accesses for the VSP.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- power-domains
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- resets
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,vsp1
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then:
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properties:
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renesas,fcp: false
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else:
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required:
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- renesas,fcp
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a07g044-vsp2
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then:
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properties:
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clocks:
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minItems: 3
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required:
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- clock-names
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names: false
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examples:
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# R8A7790 (R-Car H2) VSP1-S
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- |
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7790-sysc.h>
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vsp@fe928000 {
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compatible = "renesas,vsp1";
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reg = <0xfe928000 0x8000>;
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interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 131>;
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 131>;
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};
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# R8A77951 (R-Car H3) VSP2-BC
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- |
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7795-sysc.h>
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vsp@fe920000 {
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compatible = "renesas,vsp2";
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reg = <0xfe920000 0x8000>;
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interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 624>;
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power-domains = <&sysc R8A7795_PD_A3VP>;
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resets = <&cpg 624>;
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renesas,fcp = <&fcpvb1>;
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};
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...
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