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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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6aa5f5887d
Document the IRIS video decoder/encoder accelerator found in the QCS8300 platform. It belongs to same iris v3 family as that of SM8550 but is a downscaled version of SM8550. It has 2 frame processing hardware blocks while SM8550 has 4. Thereby QCS8300 have fewer capabilities than those of SM8550. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vikash Garodia <quic_vgarodia@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
188 lines
4.6 KiB
YAML
188 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm iris video encode and decode accelerators
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maintainers:
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- Vikash Garodia <quic_vgarodia@quicinc.com>
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- Dikshita Agarwal <quic_dikshita@quicinc.com>
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description:
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The iris video processing unit is a video encode and decode accelerator
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present on Qualcomm platforms.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,sa8775p-iris
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- const: qcom,sm8550-iris
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- enum:
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- qcom,qcs8300-iris
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- qcom,sm8550-iris
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- qcom,sm8650-iris
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power-domains:
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maxItems: 4
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power-domain-names:
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items:
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- const: venus
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- const: vcodec0
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- const: mxc
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- const: mmcx
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: iface
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- const: core
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- const: vcodec0_core
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: cpu-cfg
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- const: video-mem
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resets:
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minItems: 1
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maxItems: 3
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reset-names:
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minItems: 1
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items:
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- const: bus
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- const: xo
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- const: core
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iommus:
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maxItems: 2
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dma-coherent: true
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operating-points-v2: true
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opp-table:
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type: object
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required:
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- compatible
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- power-domain-names
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- interconnects
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- interconnect-names
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- resets
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- reset-names
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- iommus
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- dma-coherent
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allOf:
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- $ref: qcom,venus-common.yaml#
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- if:
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properties:
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compatible:
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enum:
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- qcom,sm8650-iris
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then:
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properties:
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resets:
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minItems: 3
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reset-names:
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minItems: 3
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else:
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properties:
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resets:
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maxItems: 1
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reset-names:
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maxItems: 1
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sm8550-gcc.h>
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#include <dt-bindings/clock/qcom,sm8450-videocc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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video-codec@aa00000 {
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compatible = "qcom,sm8550-iris";
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reg = <0x0aa00000 0xf0000>;
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
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<&videocc VIDEO_CC_MVS0_GDSC>,
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<&rpmhpd RPMHPD_MXC>,
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<&rpmhpd RPMHPD_MMCX>;
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power-domain-names = "venus", "vcodec0", "mxc", "mmcx";
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clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
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<&videocc VIDEO_CC_MVS0C_CLK>,
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<&videocc VIDEO_CC_MVS0_CLK>;
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clock-names = "iface", "core", "vcodec0_core";
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interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>,
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<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "cpu-cfg", "video-mem";
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memory-region = <&video_mem>;
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resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
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reset-names = "bus";
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iommus = <&apps_smmu 0x1940 0x0000>,
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<&apps_smmu 0x1947 0x0000>;
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dma-coherent;
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operating-points-v2 = <&iris_opp_table>;
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iris_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-240000000 {
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opp-hz = /bits/ 64 <240000000>;
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required-opps = <&rpmhpd_opp_svs>,
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<&rpmhpd_opp_low_svs>;
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};
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opp-338000000 {
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opp-hz = /bits/ 64 <338000000>;
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required-opps = <&rpmhpd_opp_svs>,
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<&rpmhpd_opp_svs>;
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};
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opp-366000000 {
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opp-hz = /bits/ 64 <366000000>;
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required-opps = <&rpmhpd_opp_svs_l1>,
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<&rpmhpd_opp_svs_l1>;
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};
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opp-444000000 {
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opp-hz = /bits/ 64 <444000000>;
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required-opps = <&rpmhpd_opp_turbo>,
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<&rpmhpd_opp_turbo>;
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};
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opp-533333334 {
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opp-hz = /bits/ 64 <533333334>;
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required-opps = <&rpmhpd_opp_turbo_l1>,
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<&rpmhpd_opp_turbo_l1>;
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};
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};
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};
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...
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