linux-loongson/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
Krzysztof Kozlowski c5aa327e10 media: dt-bindings: trivial white-space and example cleanup
Minor cleanups without funcitonal impact:
 - There should not be an empty blank line after SPDX tag,
 - Convention is to indent DTS examples in coding style with 2- or
   4-space indentation (4 is preferred),
 - Drop unused labels in DTS examples.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
2025-01-07 12:21:44 +01:00

69 lines
1.6 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
maintainers:
- Philipp Zabel <p.zabel@pengutronix.de>
description:
Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.
properties:
compatible:
oneOf:
- const: nxp,imx8mq-vpu
deprecated: true
- const: nxp,imx8mq-vpu-g1
- const: nxp,imx8mq-vpu-g2
- const: nxp,imx8mm-vpu-g1
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
video-codec@38300000 {
compatible = "nxp,imx8mq-vpu-g1";
reg = <0x38300000 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
};
- |
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
video-codec@38300000 {
compatible = "nxp,imx8mq-vpu-g2";
reg = <0x38310000 0x10000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
};