mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00
223fc68d31
Revise the description of MediaTek video decoder to improve wording, fix typos, simplify diagram, and extend the pipeline architecture used in newer MediaTek SoCs (MT8186 and MT8188). Signed-off-by: Fei Shao <fshao@chromium.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
286 lines
9.4 KiB
YAML
286 lines
9.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: MediaTek Video Decode Accelerator With Multi Hardware
|
|
|
|
maintainers:
|
|
- Yunfei Dong <yunfei.dong@mediatek.com>
|
|
|
|
description: |
|
|
MediaTek Video Decode Accelerator is the video decoding hardware present in
|
|
MediaTek SoCs that supports high-resolution decoding functionalities.
|
|
It consists of parent and child nodes.
|
|
|
|
The decoder hardware block diagram is shown below:
|
|
|
|
+------------------------------------------------+------------------------------+
|
|
| | |
|
|
| input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer |
|
|
| || || | || |
|
|
+--------------||-----------||-------------------+-------||---------------------+
|
|
LAT Workqueue | Core Workqueue <parent>
|
|
---------------||-----------||-------------------|-------||----------------------
|
|
||<----------||---------HW index--------->|| <child>
|
|
\/ \/ \/
|
|
+-------------------------------------------------------------+
|
|
| enable/disable |
|
|
| clk power irq iommu |
|
|
| (lat/lat-soc/core0/core1) |
|
|
+-------------------------------------------------------------+
|
|
|
|
The child nodes represent the individual hardware blocks within the decoding
|
|
pipeline, such as LAT-SoC, LAT and Core.
|
|
Each child node is responsible for managing the dedicated resources of the
|
|
hardware, such as clocks, power domains, interrupts and IOMMUs.
|
|
|
|
The parent node is a central point of control for the child nodes.
|
|
It identifies the specific video decoding pipeline architecture used by the
|
|
SoC, manages the shared resources like workqueues and platform data, and
|
|
handles V4L2 API calls on behalf of the underlying hardware.
|
|
|
|
The parent utilizes two workqueues to manage the decoding process.
|
|
1. LAT Workqueue, for LAT-SoC and LAT decoder:
|
|
Its workers take input bitstream and LAT buffer, enable the hardware for
|
|
decoding tasks, write the result to LAT buffer, and disable the hardware
|
|
after the LAT decoding is done.
|
|
2. Core Workqueue, for Core decoder:
|
|
Its workers take LAT buffer and output buffer, enable the hardware for
|
|
decoding tasks, write the result to output buffer, and disable the hardware
|
|
after the Core decoding is done.
|
|
|
|
These hardware decode each frame cyclically.
|
|
|
|
The hardware might be associated with different SMI-common devices.
|
|
To prevent IOMMU faults during DRAM access in such cases, each hardware with
|
|
the unique SMI-common device must be placed under a separate parent node in
|
|
the device tree.
|
|
|
|
LAT-SoC refers to another hardware block that connected to additional LARB
|
|
(local arbiter) ports, such as RDMA and UFO.
|
|
It requires independent power and clock control to work with LAT decoder, and
|
|
it doesn't have a dedicated interrupt.
|
|
|
|
The used video decoding pipeline architecture across various Mediatek SoC:
|
|
MT8195: LAT-SoC + LAT + Core
|
|
MT8192: LAT + Core
|
|
MT8188: LAT + Core
|
|
MT8186: Core
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- mediatek,mt8192-vcodec-dec
|
|
- mediatek,mt8186-vcodec-dec
|
|
- mediatek,mt8188-vcodec-dec
|
|
- mediatek,mt8195-vcodec-dec
|
|
|
|
reg:
|
|
minItems: 1
|
|
items:
|
|
- description: VDEC_SYS register space
|
|
- description: VDEC_RACING_CTRL register space
|
|
|
|
iommus:
|
|
minItems: 1
|
|
maxItems: 32
|
|
description: |
|
|
List of the hardware port in respective IOMMU block for current Socs.
|
|
Refer to bindings/iommu/mediatek,iommu.yaml.
|
|
|
|
mediatek,scp:
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
|
description: |
|
|
The node of system control processor (SCP), using
|
|
the remoteproc & rpmsg framework.
|
|
|
|
"#address-cells":
|
|
const: 2
|
|
|
|
"#size-cells":
|
|
const: 2
|
|
|
|
ranges: true
|
|
|
|
# Required child node:
|
|
patternProperties:
|
|
'^video-codec@[0-9a-f]+$':
|
|
type: object
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- mediatek,mtk-vcodec-core
|
|
- mediatek,mtk-vcodec-lat
|
|
- mediatek,mtk-vcodec-lat-soc
|
|
|
|
reg:
|
|
maxItems: 1
|
|
description: VDEC_MISC register space
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
iommus:
|
|
minItems: 1
|
|
maxItems: 32
|
|
description: |
|
|
List of the hardware port in respective IOMMU block for current Socs.
|
|
Refer to bindings/iommu/mediatek,iommu.yaml.
|
|
|
|
clocks:
|
|
minItems: 4
|
|
maxItems: 5
|
|
|
|
clock-names:
|
|
minItems: 4
|
|
maxItems: 5
|
|
|
|
assigned-clocks:
|
|
maxItems: 1
|
|
|
|
assigned-clock-parents:
|
|
maxItems: 1
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- iommus
|
|
- clocks
|
|
- clock-names
|
|
- assigned-clocks
|
|
- assigned-clock-parents
|
|
- power-domains
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- iommus
|
|
- mediatek,scp
|
|
- ranges
|
|
|
|
if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- mediatek,mtk-vcodec-core
|
|
- mediatek,mtk-vcodec-lat
|
|
|
|
then:
|
|
required:
|
|
- interrupts
|
|
|
|
allOf:
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- mediatek,mt8192-vcodec-dec
|
|
then:
|
|
properties:
|
|
clock-names:
|
|
items:
|
|
- const: sel
|
|
- const: soc-vdec
|
|
- const: soc-lat
|
|
- const: vdec
|
|
- const: top
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- mediatek,mt8195-vcodec-dec
|
|
then:
|
|
properties:
|
|
clock-names:
|
|
items:
|
|
- const: sel
|
|
- const: vdec
|
|
- const: lat
|
|
- const: top
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/memory/mt8192-larb-port.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/clock/mt8192-clk.h>
|
|
#include <dt-bindings/power/mt8192-power.h>
|
|
|
|
bus@16000000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0 0x16000000 0x16000000 0 0x40000>;
|
|
|
|
video-codec@16000000 {
|
|
compatible = "mediatek,mt8192-vcodec-dec";
|
|
mediatek,scp = <&scp>;
|
|
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0 0 0 0x16000000 0 0x40000>;
|
|
reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
|
|
video-codec@10000 {
|
|
compatible = "mediatek,mtk-vcodec-lat";
|
|
reg = <0 0x10000 0 0x800>;
|
|
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
|
|
<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
|
|
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
|
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
|
|
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
|
|
<&vdecsys_soc CLK_VDEC_SOC_LARB1>,
|
|
<&topckgen CLK_TOP_MAINPLL_D4>;
|
|
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
|
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
|
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
|
|
};
|
|
|
|
video-codec@25000 {
|
|
compatible = "mediatek,mtk-vcodec-core";
|
|
reg = <0 0x25000 0 0x1000>;
|
|
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
|
|
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
|
|
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
|
|
<&vdecsys CLK_VDEC_VDEC>,
|
|
<&vdecsys CLK_VDEC_LAT>,
|
|
<&vdecsys CLK_VDEC_LARB1>,
|
|
<&topckgen CLK_TOP_MAINPLL_D4>;
|
|
clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
|
|
assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
|
|
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
|
|
};
|
|
};
|
|
};
|