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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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Add compatible strings for the FG, HDR, RSZ, STITCH, TCC, TDSHP and WROT hardware components found in MediaTek's MT8188 SoC. This hardware is compatible with MT8195. Acked-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241218105320.38980-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
66 lines
1.7 KiB
YAML
66 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Media Data Path 3 HDR
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maintainers:
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- Matthias Brugger <matthias.bgg@gmail.com>
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- Moudy Ho <moudy.ho@mediatek.com>
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description:
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A Media Data Path 3 (MDP3) component used to perform conversion from
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High Dynamic Range (HDR) to Standard Dynamic Range (SDR).
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt8195-mdp3-hdr
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- items:
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- const: mediatek,mt8188-mdp3-hdr
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- const: mediatek,mt8195-mdp3-hdr
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reg:
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maxItems: 1
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mediatek,gce-client-reg:
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description:
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The register of display function block to be set by gce. There are 4 arguments,
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such as gce node, subsys id, offset and register size. The subsys id that is
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mapping to the register of display function blocks is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h of each chips.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle of GCE
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- description: GCE subsys id
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- description: register offset
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- description: register size
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- mediatek,gce-client-reg
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <dt-bindings/gce/mt8195-gce.h>
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display@14004000 {
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compatible = "mediatek,mt8195-mdp3-hdr";
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reg = <0x14004000 0x1000>;
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mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>;
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clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
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};
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