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dacd54eb2d
Add dt-bindings for Imagination E5010 JPEG Encoder [1] which is implemented as stateful V4L2 M2M driver. The device supports baseline encoding with two different quantization tables and compression ratio as demanded. Minimum resolution supported is 64x64 and Maximum resolution supported is 8192x8192. Link: https://www.ti.com/lit/pdf/spruj16 [1] (Section 7.6 JPEG Encoder) Co-developed-by: David Huang <d-huang@ti.com> Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
76 lines
1.7 KiB
YAML
76 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/img,e5010-jpeg-enc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Imagination E5010 JPEG Encoder
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maintainers:
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- Devarsh Thakkar <devarsht@ti.com>
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description: |
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The E5010 is a JPEG encoder from Imagination Technologies implemented on
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TI's AM62A SoC. It is capable of real time encoding of YUV420 and YUV422
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inputs to JPEG and M-JPEG. It supports baseline JPEG Encoding up to
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8Kx8K resolution.
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properties:
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compatible:
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oneOf:
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- items:
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- const: ti,am62a-jpeg-enc
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- const: img,e5010-jpeg-enc
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- const: img,e5010-jpeg-enc
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reg:
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items:
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- description: The E5010 core register region
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- description: The E5010 mmu register region
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reg-names:
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items:
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- const: core
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- const: mmu
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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jpeg-encoder@fd20000 {
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compatible = "img,e5010-jpeg-enc";
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reg = <0x00 0xfd20000 0x00 0x100>,
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<0x00 0xfd20200 0x00 0x200>;
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reg-names = "core", "mmu";
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clocks = <&k3_clks 201 0>;
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power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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