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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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48dbb76cef
Convert binding doc imx.txt to yaml format. Create two yaml files: fsl,imx6-mipi-csi2.yaml and fsl,imx-capture-subsystem.yaml. Additional changes: - add example for fsl,imx6-mipi-csi2 - add irq err1 and err2 description - update MAINTAINERS Signed-off-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> [hverkuil: drop empty line at the end of the yaml files]
144 lines
3.4 KiB
YAML
144 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/fsl,imx6-mipi-csi2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MIPI CSI-2 Receiver core in the i.MX SoC
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description:
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This is the device node for the MIPI CSI-2 Receiver core in the i.MX
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SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
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combined with a D-PHY core mixed into the same register block. In
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addition this device consists of an i.MX-specific "CSI2IPU gasket"
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glue logic, also controlled from the same register block. The CSI2IPU
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gasket demultiplexes the four virtual channel streams from the host
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controller's 32-bit output image bus onto four 16-bit parallel busses
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to the i.MX IPU CSIs.
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maintainers:
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- Frank Li <Frank.Li@nxp.com>
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properties:
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compatible:
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const: fsl,imx6-mipi-csi2
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reg:
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maxItems: 1
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clocks:
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items:
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- description: hsi_tx (the D-PHY clock)
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- description: video_27m (D-PHY PLL reference clock)
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- description: eim_podf;
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clock-names:
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items:
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- const: dphy
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- const: ref
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- const: pix
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interrupts:
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items:
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- description: CSI-2 ERR1 irq
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- description: CSI-2 ERR2 irq
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port node, single endpoint describing the CSI-2 transmitter.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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clock-lanes:
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const: 0
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data-lanes:
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minItems: 1
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items:
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- const: 1
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- const: 2
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- const: 3
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- const: 4
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required:
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- data-lanes
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patternProperties:
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'^port@[1-4]$':
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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ports 1 through 4 are output ports connecting with parallel bus sink
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endpoint nodes and correspond to the four MIPI CSI-2 virtual channel
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outputs.
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properties:
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endpoint@0:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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endpoint@1:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx6qdl-clock.h>
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mipi@21dc000 {
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compatible = "fsl,imx6-mipi-csi2";
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reg = <0x021dc000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clks IMX6QDL_CLK_HSI_TX>,
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<&clks IMX6QDL_CLK_VIDEO_27M>,
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<&clks IMX6QDL_CLK_EIM_PODF>;
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clock-names = "dphy", "ref", "pix";
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&ov5640_to_mipi_csi2>;
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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endpoint@0 {
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reg = <0>;
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remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
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};
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endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
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};
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};
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};
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