mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-03 17:51:23 +00:00
f45b2949b1
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.
Fix the name in the driver, header and device-tree.
Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-By: Icenowy Zheng <uwu@icenowy.me>
Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
138 lines
2.8 KiB
YAML
138 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A31 MIPI CSI-2
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maintainers:
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- Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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properties:
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compatible:
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oneOf:
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- const: allwinner,sun6i-a31-mipi-csi2
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- items:
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- const: allwinner,sun8i-v3s-mipi-csi2
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- const: allwinner,sun6i-a31-mipi-csi2
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: bus
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- const: mod
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phys:
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maxItems: 1
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description: MIPI D-PHY
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phy-names:
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items:
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- const: dphy
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resets:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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description: Input port, connect to a MIPI CSI-2 sensor
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properties:
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reg:
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const: 0
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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unevaluatedProperties: false
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output port, connect to a CSI controller
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- phys
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- phy-names
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- resets
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-v3s-ccu.h>
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#include <dt-bindings/reset/sun8i-v3s-ccu.h>
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mipi_csi2: csi@1cb1000 {
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compatible = "allwinner,sun8i-v3s-mipi-csi2",
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"allwinner,sun6i-a31-mipi-csi2";
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reg = <0x01cb1000 0x1000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CSI>,
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<&ccu CLK_CSI_SCLK>;
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clock-names = "bus", "mod";
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resets = <&ccu RST_BUS_CSI>;
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phys = <&dphy>;
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phy-names = "dphy";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_csi2_in: port@0 {
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reg = <0>;
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mipi_csi2_in_ov5648: endpoint {
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&ov5648_out_mipi_csi2>;
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};
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};
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mipi_csi2_out: port@1 {
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reg = <1>;
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mipi_csi2_out_csi0: endpoint {
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remote-endpoint = <&csi0_in_mipi_csi2>;
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};
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};
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};
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};
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...
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