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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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f45b2949b1
The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.
Fix the name in the driver, header and device-tree.
Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Reviewed-By: Icenowy Zheng <uwu@icenowy.me>
Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
144 lines
3.1 KiB
YAML
144 lines
3.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A31 CMOS Sensor Interface (CSI)
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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compatible:
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enum:
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- allwinner,sun6i-a31-csi
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- allwinner,sun8i-a83t-csi
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- allwinner,sun8i-h3-csi
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- allwinner,sun8i-v3s-csi
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- allwinner,sun50i-a64-csi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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- description: DRAM Clock
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clock-names:
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items:
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- const: bus
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- const: mod
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- const: ram
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resets:
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maxItems: 1
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port:
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$ref: /schemas/graph.yaml#/$defs/port-base
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description: Parallel input port, connect to a parallel sensor
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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bus-width:
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enum: [ 8, 10, 12, 16 ]
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pclk-sample: true
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hsync-active: true
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vsync-active: true
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required:
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- bus-width
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unevaluatedProperties: false
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: "#/properties/port"
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: MIPI CSI-2 bridge input port
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port@2:
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$ref: /schemas/graph.yaml#/properties/port
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description: Internal output port to the ISP
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anyOf:
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- required:
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- port@0
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- required:
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- port@1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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oneOf:
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- required:
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- ports
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- required:
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- port
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun8i-v3s-ccu.h>
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#include <dt-bindings/reset/sun8i-v3s-ccu.h>
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csi1: csi@1cb4000 {
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compatible = "allwinner,sun8i-v3s-csi";
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reg = <0x01cb4000 0x1000>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_CSI>,
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<&ccu CLK_CSI_SCLK>,
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<&ccu CLK_DRAM_CSI>;
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clock-names = "bus",
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"mod",
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"ram";
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resets = <&ccu RST_BUS_CSI>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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/* Parallel bus endpoint */
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csi1_ep: endpoint {
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remote-endpoint = <&adv7611_ep>;
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bus-width = <16>;
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/*
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* If hsync-active/vsync-active are missing,
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* embedded BT.656 sync is used.
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*/
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hsync-active = <0>; /* Active low */
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vsync-active = <0>; /* Active low */
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pclk-sample = <1>; /* Rising */
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};
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};
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};
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};
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...
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