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fca8d64001
Introduce the mailbox module for CV18XX series SoC, which is responsible for interchanging messages between asymmetric processors. Signed-off-by: Yuntao Dai <d1581209858@live.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
61 lines
1.4 KiB
YAML
61 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Sophgo CV1800/SG2000 mailbox controller
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maintainers:
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- Yuntao Dai <d1581209858@live.com>
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- Junhui Liu <junhui.liu@pigmoral.tech>
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description:
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Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each
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shipping an 8-byte FIFO. Any processor can write to an arbitrary channel
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and raise interrupts to receivers. Sending messages to itself is also
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supported.
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properties:
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compatible:
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const: sophgo,cv1800b-mailbox
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 2
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description: |
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<&phandle channel target>
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phandle : Label name of mailbox controller
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channel : 0-7, Channel index
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target : 0-3, Target processor ID
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Sophgo CV1800/SG2000 SoCs include the following processors, numbered as:
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<0> Cortex-A53 (Only available on CV181X/SG200X)
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<1> C906B
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<2> C906L
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<3> 8051
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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mailbox@1900000 {
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compatible = "sophgo,cv1800b-mailbox";
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reg = <0x01900000 0x1000>;
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interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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