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6e7c4cc55d
Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
50 lines
1.1 KiB
YAML
50 lines
1.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
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maintainers:
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- Sibi Sankar <quic_sibis@quicinc.com>
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description:
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The CPUSS Control Processor (CPUCP) mailbox controller enables communication
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between AP and CPUCP by acting as a doorbell between them.
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properties:
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compatible:
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items:
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- const: qcom,x1e80100-cpucp-mbox
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reg:
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items:
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- description: CPUCP rx register region
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- description: CPUCP tx register region
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox@17430000 {
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compatible = "qcom,x1e80100-cpucp-mbox";
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reg = <0x17430000 0x10000>, <0x18830000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
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