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af33bd58c2
Add a dt-binding for the Microchip Inter-Processor Communication (IPC) mailbox controller. Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@microchip.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
124 lines
3.4 KiB
YAML
124 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Inter-processor communication (IPC) mailbox controller
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maintainers:
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- Valentina Fernandez <valentina.fernandezalanis@microchip.com>
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description:
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The Microchip Inter-processor Communication (IPC) facilitates
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message passing between processors using an interrupt signaling
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mechanism.
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properties:
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compatible:
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oneOf:
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- description:
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Intended for use by software running in supervisor privileged
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mode (s-mode). This SBI interface is compatible with the Mi-V
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Inter-hart Communication (IHC) IP.
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const: microchip,sbi-ipc
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- description:
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Intended for use by the SBI implementation in machine mode
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(m-mode), this compatible string is for the MIV_IHC Soft-IP.
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const: microchip,miv-ihc-rtl-v2
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 5
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interrupt-names:
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minItems: 1
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maxItems: 5
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items:
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enum:
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- hart-0
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- hart-1
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- hart-2
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- hart-3
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- hart-4
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- hart-5
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"#mbox-cells":
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description: >
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For "microchip,sbi-ipc", the cell represents the global "logical"
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channel IDs. The meaning of channel IDs are platform firmware dependent.
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For "microchip,miv-ihc-rtl-v2", the cell represents the physical
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channel and does not vary based on the platform firmware.
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const: 1
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microchip,ihc-chan-disabled-mask:
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description: >
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Represents the enable/disable state of the bi-directional IHC
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channels within the MIV-IHC IP configuration.
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A bit set to '1' indicates that the corresponding channel is disabled,
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and any read or write operations to that channel will return zero.
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A bit set to '0' indicates that the corresponding channel is enabled
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and will be accessible through its dedicated address range registers.
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The actual enable/disable state of each channel is determined by the
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IP block’s configuration.
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$ref: /schemas/types.yaml#/definitions/uint16
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maximum: 0x7fff
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default: 0
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required:
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- compatible
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- interrupts
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- interrupt-names
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- "#mbox-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: microchip,sbi-ipc
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then:
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properties:
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reg:
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not: {}
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description:
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The 'microchip,sbi-ipc' operates in a programming model
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that does not require memory-mapped I/O (MMIO) registers
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since it uses SBI ecalls provided by the m-mode/firmware
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SBI implementation to access hardware registers.
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microchip,ihc-chan-disabled-mask: false
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else:
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required:
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- reg
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- microchip,ihc-chan-disabled-mask
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additionalProperties: false
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examples:
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- |
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mailbox {
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compatible = "microchip,sbi-ipc";
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>;
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interrupt-names = "hart-1", "hart-2", "hart-3";
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#mbox-cells = <1>;
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};
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- |
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mailbox@50000000 {
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compatible = "microchip,miv-ihc-rtl-v2";
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microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
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reg = <0x50000000 0x1c000>;
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interrupt-parent = <&plic>;
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interrupts = <180>, <179>, <178>;
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interrupt-names = "hart-1", "hart-2", "hart-3";
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#mbox-cells = <1>;
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};
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