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56cf1209f6
Add bindings for the Samsung Exynos Mailbox Controller. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
70 lines
1.6 KiB
YAML
70 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright 2024 Linaro Ltd.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos Mailbox Controller
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maintainers:
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- Tudor Ambarus <tudor.ambarus@linaro.org>
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description:
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The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
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bits for hardware interrupt generation and a shared register for passing
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mailbox messages. When the controller is used by the ACPM interface
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the shared register is ignored and the mailbox controller acts as a doorbell.
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The controller just raises the interrupt to the firmware after the
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ACPM interface has written the message to SRAM.
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properties:
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compatible:
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const: google,gs101-mbox
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: pclk
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interrupts:
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description: IRQ line for the RX mailbox.
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maxItems: 1
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'#mbox-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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- '#mbox-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/google,gs101.h>
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ap2apm_mailbox: mailbox@17610000 {
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compatible = "google,gs101-mbox";
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reg = <0x17610000 0x1000>;
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clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
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clock-names = "pclk";
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
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#mbox-cells = <0>;
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};
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};
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