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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7d33dd2d0e
Introduce the mailbox module for AST27XX series SoC, which is responsible for interchanging messages between asymmetric processors. Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
69 lines
1.8 KiB
YAML
69 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mailbox/aspeed,ast2700-mailbox.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ASPEED AST2700 mailbox controller
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maintainers:
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- Jammy Huang <jammy_huang@aspeedtech.com>
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description: >
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ASPEED AST2700 has multiple processors that need to communicate with each
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other. The mailbox controller provides a way for these processors to send
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messages to each other. It is a hardware-based inter-processor communication
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mechanism that allows processors to send and receive messages through
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dedicated channels.
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The mailbox's tx/rx are independent, meaning that one processor can send a
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message while another processor is receiving a message simultaneously.
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There are 4 channels available for both tx and rx operations. Each channel
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has a FIFO buffer that can hold messages of a fixed size (32 bytes in this
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case).
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The mailbox controller also supports interrupt generation, allowing
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processors to notify each other when a message is available or when an event
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occurs.
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properties:
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compatible:
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const: aspeed,ast2700-mailbox
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reg:
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items:
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- description: TX control register
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- description: RX control register
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reg-names:
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items:
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- const: tx
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- const: rx
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interrupts:
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maxItems: 1
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"#mbox-cells":
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const: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- "#mbox-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mailbox@12c1c200 {
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compatible = "aspeed,ast2700-mailbox";
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reg = <0x12c1c200 0x100>, <0x12c1c300 0x100>;
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reg-names = "tx", "rx";
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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};
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