mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
ac1207f516
The firmware on SDM845-based Cheza boards did not provide the same level of feature support for SMMUs (particularly around the Adreno GPU integration). Now that Cheza is being removed from the kernel (almost none exist at this point in time), retire the entry as well. Most notably, it's not being marked as deprecated instead, as there is no indication that any more of those ~7 year old devboards will be built. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/20250716-topic-goodnight_cheza-v2-3-6fa8d3261813@oss.qualcomm.com Signed-off-by: Will Deacon <will@kernel.org>
711 lines
21 KiB
YAML
711 lines
21 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM System MMU Architecture Implementation
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maintainers:
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- Will Deacon <will@kernel.org>
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- Robin Murphy <Robin.Murphy@arm.com>
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description: |+
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ARM SoCs may contain an implementation of the ARM System Memory
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Management Unit Architecture, which can be used to provide 1 or 2 stages
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of address translation to bus masters external to the CPU.
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The SMMU may also raise interrupts in response to various fault
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conditions.
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properties:
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$nodename:
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pattern: "^iommu@[0-9a-f]*"
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compatible:
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oneOf:
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- description: Qcom SoCs implementing "arm,smmu-v2"
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items:
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- enum:
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- qcom,msm8996-smmu-v2
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- qcom,msm8998-smmu-v2
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- qcom,sdm630-smmu-v2
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- qcom,sm6375-smmu-v2
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- const: qcom,smmu-v2
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- description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
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items:
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- enum:
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- qcom,milos-smmu-500
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- qcom,qcm2290-smmu-500
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- qcom,qcs615-smmu-500
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- qcom,qcs8300-smmu-500
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- qcom,qdu1000-smmu-500
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- qcom,sa8255p-smmu-500
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- qcom,sa8775p-smmu-500
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- qcom,sar2130p-smmu-500
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- qcom,sc7180-smmu-500
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- qcom,sc7280-smmu-500
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- qcom,sc8180x-smmu-500
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- qcom,sc8280xp-smmu-500
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- qcom,sdm670-smmu-500
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- qcom,sdm845-smmu-500
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- qcom,sdx55-smmu-500
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- qcom,sdx65-smmu-500
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- qcom,sdx75-smmu-500
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- qcom,sm6115-smmu-500
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- qcom,sm6125-smmu-500
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- qcom,sm6350-smmu-500
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- qcom,sm6375-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- qcom,sm8450-smmu-500
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- qcom,sm8550-smmu-500
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- qcom,sm8650-smmu-500
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- qcom,sm8750-smmu-500
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- qcom,x1e80100-smmu-500
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- const: qcom,smmu-500
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- const: arm,mmu-500
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- description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
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deprecated: true
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items:
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# Do not add additional SoC to this list. Instead use two previous lists.
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- enum:
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- qcom,qcm2290-smmu-500
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- qcom,sc7180-smmu-500
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- qcom,sc7280-smmu-500
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- qcom,sc8180x-smmu-500
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- qcom,sc8280xp-smmu-500
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- qcom,sdm845-smmu-500
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- qcom,sm6115-smmu-500
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- qcom,sm6350-smmu-500
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- qcom,sm6375-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- qcom,sm8450-smmu-500
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
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items:
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- enum:
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- qcom,milos-smmu-500
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- qcom,qcm2290-smmu-500
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- qcom,qcs615-smmu-500
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- qcom,qcs8300-smmu-500
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- qcom,sa8255p-smmu-500
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- qcom,sa8775p-smmu-500
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- qcom,sar2130p-smmu-500
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- qcom,sc7280-smmu-500
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- qcom,sc8180x-smmu-500
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- qcom,sc8280xp-smmu-500
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- qcom,sm6115-smmu-500
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- qcom,sm6125-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- qcom,sm8450-smmu-500
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- qcom,sm8550-smmu-500
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- qcom,sm8650-smmu-500
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- qcom,sm8750-smmu-500
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- qcom,x1e80100-smmu-500
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- const: qcom,adreno-smmu
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- const: qcom,smmu-500
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
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deprecated: true
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items:
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# Do not add additional SoC to this list. Instead use previous list.
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- enum:
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- qcom,sc7280-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- const: qcom,adreno-smmu
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "arm,smmu-v2"
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items:
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- enum:
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- qcom,msm8996-smmu-v2
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- qcom,sc7180-smmu-v2
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- qcom,sdm630-smmu-v2
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- qcom,sdm670-smmu-v2
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- qcom,sdm845-smmu-v2
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- qcom,sm6350-smmu-v2
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- qcom,sm7150-smmu-v2
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- const: qcom,adreno-smmu
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- const: qcom,smmu-v2
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- description: Marvell SoCs implementing "arm,mmu-500"
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items:
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- const: marvell,ap806-smmu-500
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- const: arm,mmu-500
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- description: NVIDIA SoCs that require memory controller interaction
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and may program multiple ARM MMU-500s identically with the memory
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controller interleaving translations between multiple instances
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for improved performance.
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items:
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- enum:
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- nvidia,tegra186-smmu
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- nvidia,tegra194-smmu
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- nvidia,tegra234-smmu
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- const: nvidia,smmu-500
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- items:
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- const: arm,mmu-500
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- const: arm,smmu-v2
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- items:
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- enum:
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- arm,mmu-400
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- arm,mmu-401
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- const: arm,smmu-v1
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- enum:
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- arm,smmu-v1
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- arm,smmu-v2
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- arm,mmu-400
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- arm,mmu-401
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- arm,mmu-500
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- cavium,smmu-v2
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reg:
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minItems: 1
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maxItems: 2
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'#global-interrupts':
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description: The number of global interrupts exposed by the device.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
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'#iommu-cells':
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enum: [ 1, 2 ]
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description: |
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See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
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value of 1, each IOMMU specifier represents a distinct stream ID emitted
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by that device into the relevant SMMU.
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SMMUs with stream matching support and complex masters may use a value of
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2, where the second cell of the IOMMU specifier represents an SMR mask to
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combine with the ID in the first cell. Care must be taken to ensure the
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set of matched IDs does not result in conflicts.
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interrupts:
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minItems: 1
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maxItems: 388 # 260 plus 128 contexts
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description: |
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Interrupt list, with the first #global-interrupts entries corresponding to
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the global interrupts and any following entries corresponding to context
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interrupts, specified in order of their indexing by the SMMU.
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For SMMUv2 implementations, there must be exactly one interrupt per
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context bank. In the case of a single, combined interrupt, it must be
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listed multiple times.
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dma-coherent:
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description: |
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Present if page table walks made by the SMMU are cache coherent with the
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CPU.
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NOTE: this only applies to the SMMU itself, not masters connected
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upstream of the SMMU.
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calxeda,smmu-secure-config-access:
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type: boolean
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description:
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Enable proper handling of buggy implementations that always use secure
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access to SMMU configuration registers. In this case non-secure aliases of
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secure registers have to be used during SMMU configuration.
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stream-match-mask:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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For SMMUs supporting stream matching and using #iommu-cells = <1>,
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specifies a mask of bits to ignore when matching stream IDs (e.g. this may
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be programmed into the SMRn.MASK field of every stream match register
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used). For cases where it is desirable to ignore some portion of every
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Stream ID (e.g. for certain MMU-500 configurations given globally unique
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input IDs). This property is not valid for SMMUs using stream indexing, or
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using stream matching with #iommu-cells = <2>, and may be ignored if
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present in such cases.
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clock-names:
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minItems: 1
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maxItems: 7
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clocks:
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minItems: 1
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maxItems: 7
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power-domains:
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minItems: 1
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maxItems: 3
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nvidia,memory-controller:
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description: |
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A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
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The memory controller needs to be programmed with a mapping of memory
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client IDs to ARM SMMU stream IDs.
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If this property is absent, the mapping programmed by early firmware
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will be used and it is not guaranteed that IOMMU translations will be
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enabled for any given device.
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$ref: /schemas/types.yaml#/definitions/phandle
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required:
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- compatible
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- reg
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- '#global-interrupts'
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- '#iommu-cells'
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- interrupts
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra186-smmu
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- nvidia,tegra194-smmu
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- nvidia,tegra234-smmu
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then:
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properties:
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reg:
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minItems: 1
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maxItems: 2
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# The reference to the memory controller is required to ensure that the
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# memory client to stream ID mapping can be done synchronously with the
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# IOMMU attachment.
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required:
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- nvidia,memory-controller
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else:
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properties:
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reg:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8998-smmu-v2
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- qcom,sdm630-smmu-v2
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then:
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anyOf:
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- properties:
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clock-names:
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items:
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- const: bus
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clocks:
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items:
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- description: bus clock required for downstream bus access and for
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the smmu ptw
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- properties:
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clock-names:
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items:
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- const: iface
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- const: mem
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- const: mem_iface
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clocks:
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items:
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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- description: bus clock required for memory access
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- description: bus clock required for GPU memory access
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- properties:
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clock-names:
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items:
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- const: iface-mm
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- const: iface-smmu
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- const: bus-smmu
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clocks:
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items:
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- description: interface clock required to access mnoc's registers
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through the TCU's programming interface.
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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- description: bus clock required for the smmu ptw
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm6375-smmu-v2
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then:
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anyOf:
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- properties:
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clock-names:
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items:
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- const: bus
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clocks:
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items:
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- description: bus clock required for downstream bus access and for
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the smmu ptw
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- properties:
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clock-names:
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items:
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- const: iface
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- const: mem
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- const: mem_iface
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clocks:
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items:
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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- description: bus clock required for memory access
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- description: bus clock required for GPU memory access
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- properties:
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clock-names:
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items:
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- const: iface-mm
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- const: iface-smmu
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- const: bus-mm
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- const: bus-smmu
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clocks:
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items:
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- description: interface clock required to access mnoc's registers
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through the TCU's programming interface.
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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- description: bus clock required for downstream bus access
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- description: bus clock required for the smmu ptw
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,msm8996-smmu-v2
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- qcom,sc7180-smmu-v2
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- qcom,sdm845-smmu-v2
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then:
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properties:
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clock-names:
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items:
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- const: bus
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- const: iface
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clocks:
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items:
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- description: bus clock required for downstream bus access and for
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the smmu ptw
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,qcs8300-smmu-500
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- qcom,sa8775p-smmu-500
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- qcom,sc7280-smmu-500
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- qcom,sc8280xp-smmu-500
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then:
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properties:
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clock-names:
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items:
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- const: gcc_gpu_memnoc_gfx_clk
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- const: gcc_gpu_snoc_dvm_gfx_clk
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- const: gpu_cc_ahb_clk
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- const: gpu_cc_hlos1_vote_gpu_smmu_clk
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- const: gpu_cc_cx_gmu_clk
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- const: gpu_cc_hub_cx_int_clk
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- const: gpu_cc_hub_aon_clk
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clocks:
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items:
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- description: GPU memnoc_gfx clock
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- description: GPU snoc_dvm_gfx clock
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- description: GPU ahb clock
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- description: GPU hlos1_vote_GPU smmu clock
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- description: GPU cx_gmu clock
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- description: GPU hub_cx_int clock
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- description: GPU hub_aon clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sc8180x-smmu-500
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- qcom,sm6350-smmu-v2
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- qcom,sm7150-smmu-v2
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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then:
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properties:
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clock-names:
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items:
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- const: ahb
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- const: bus
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- const: iface
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clocks:
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items:
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- description: bus clock required for AHB bus access
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- description: bus clock required for downstream bus access and for
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the smmu ptw
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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|
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- if:
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properties:
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compatible:
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items:
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- enum:
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- qcom,sm8350-smmu-500
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- const: qcom,adreno-smmu
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- const: qcom,smmu-500
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- const: arm,mmu-500
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then:
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properties:
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clock-names:
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items:
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- const: bus
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- const: iface
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- const: ahb
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- const: hlos1_vote_gpu_smmu
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- const: cx_gmu
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- const: hub_cx_int
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- const: hub_aon
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clocks:
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minItems: 7
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maxItems: 7
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|
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- if:
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properties:
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compatible:
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items:
|
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- enum:
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- qcom,qcm2290-smmu-500
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- qcom,qcs615-smmu-500
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- qcom,sm6115-smmu-500
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- qcom,sm6125-smmu-500
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- const: qcom,adreno-smmu
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- const: qcom,smmu-500
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- const: arm,mmu-500
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then:
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properties:
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clock-names:
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items:
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- const: mem
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- const: hlos
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- const: iface
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clocks:
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items:
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- description: GPU memory bus clock
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- description: Voter clock required for HLOS SMMU access
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- description: Interface clock required for register access
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- if:
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properties:
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compatible:
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items:
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- const: qcom,sm8450-smmu-500
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- const: qcom,adreno-smmu
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- const: qcom,smmu-500
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- const: arm,mmu-500
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then:
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properties:
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clock-names:
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items:
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- const: gmu
|
|
- const: hub
|
|
- const: hlos
|
|
- const: bus
|
|
- const: iface
|
|
- const: ahb
|
|
|
|
clocks:
|
|
items:
|
|
- description: GMU clock
|
|
- description: GPU HUB clock
|
|
- description: HLOS vote clock
|
|
- description: GPU memory bus clock
|
|
- description: GPU SNoC bus clock
|
|
- description: GPU AHB clock
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
items:
|
|
- enum:
|
|
- qcom,milos-smmu-500
|
|
- qcom,sar2130p-smmu-500
|
|
- qcom,sm8550-smmu-500
|
|
- qcom,sm8650-smmu-500
|
|
- qcom,x1e80100-smmu-500
|
|
- const: qcom,adreno-smmu
|
|
- const: qcom,smmu-500
|
|
- const: arm,mmu-500
|
|
then:
|
|
properties:
|
|
clock-names:
|
|
items:
|
|
- const: hlos
|
|
- const: bus
|
|
- const: iface
|
|
- const: ahb
|
|
|
|
clocks:
|
|
items:
|
|
- description: HLOS vote clock
|
|
- description: GPU memory bus clock
|
|
- description: GPU SNoC bus clock
|
|
- description: GPU AHB clock
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
items:
|
|
- const: qcom,sm8750-smmu-500
|
|
- const: qcom,adreno-smmu
|
|
- const: qcom,smmu-500
|
|
- const: arm,mmu-500
|
|
then:
|
|
properties:
|
|
clock-names:
|
|
items:
|
|
- const: hlos
|
|
clocks:
|
|
items:
|
|
- description: HLOS vote clock
|
|
|
|
# Disallow clocks for all other platforms with specific compatibles
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- cavium,smmu-v2
|
|
- marvell,ap806-smmu-500
|
|
- nvidia,smmu-500
|
|
- qcom,qdu1000-smmu-500
|
|
- qcom,sa8255p-smmu-500
|
|
- qcom,sc7180-smmu-500
|
|
- qcom,sdm670-smmu-500
|
|
- qcom,sdm845-smmu-500
|
|
- qcom,sdx55-smmu-500
|
|
- qcom,sdx65-smmu-500
|
|
- qcom,sm6350-smmu-500
|
|
- qcom,sm6375-smmu-500
|
|
then:
|
|
properties:
|
|
clock-names: false
|
|
clocks: false
|
|
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: qcom,sm6375-smmu-500
|
|
then:
|
|
properties:
|
|
power-domains:
|
|
items:
|
|
- description: SNoC MMU TBU RT GDSC
|
|
- description: SNoC MMU TBU NRT GDSC
|
|
- description: SNoC TURING MMU TBU0 GDSC
|
|
|
|
required:
|
|
- power-domains
|
|
else:
|
|
properties:
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
examples:
|
|
- |+
|
|
/* SMMU with stream matching or stream indexing */
|
|
smmu1: iommu@ba5e0000 {
|
|
compatible = "arm,smmu-v1";
|
|
reg = <0xba5e0000 0x10000>;
|
|
#global-interrupts = <2>;
|
|
interrupts = <0 32 4>,
|
|
<0 33 4>,
|
|
<0 34 4>, /* This is the first context interrupt */
|
|
<0 35 4>,
|
|
<0 36 4>,
|
|
<0 37 4>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
/* device with two stream IDs, 0 and 7 */
|
|
master1 {
|
|
iommus = <&smmu1 0>,
|
|
<&smmu1 7>;
|
|
};
|
|
|
|
|
|
/* SMMU with stream matching */
|
|
smmu2: iommu@ba5f0000 {
|
|
compatible = "arm,smmu-v1";
|
|
reg = <0xba5f0000 0x10000>;
|
|
#global-interrupts = <2>;
|
|
interrupts = <0 38 4>,
|
|
<0 39 4>,
|
|
<0 40 4>, /* This is the first context interrupt */
|
|
<0 41 4>,
|
|
<0 42 4>,
|
|
<0 43 4>;
|
|
#iommu-cells = <2>;
|
|
};
|
|
|
|
/* device with stream IDs 0 and 7 */
|
|
master2 {
|
|
iommus = <&smmu2 0 0>,
|
|
<&smmu2 7 0>;
|
|
};
|
|
|
|
/* device with stream IDs 1, 17, 33 and 49 */
|
|
master3 {
|
|
iommus = <&smmu2 1 0x30>;
|
|
};
|
|
|
|
|
|
/* ARM MMU-500 with 10-bit stream ID input configuration */
|
|
smmu3: iommu@ba600000 {
|
|
compatible = "arm,mmu-500", "arm,smmu-v2";
|
|
reg = <0xba600000 0x10000>;
|
|
#global-interrupts = <2>;
|
|
interrupts = <0 44 4>,
|
|
<0 45 4>,
|
|
<0 46 4>, /* This is the first context interrupt */
|
|
<0 47 4>,
|
|
<0 48 4>,
|
|
<0 49 4>;
|
|
#iommu-cells = <1>;
|
|
/* always ignore appended 5-bit TBU number */
|
|
stream-match-mask = <0x7c00>;
|
|
};
|
|
|
|
bus {
|
|
/* bus whose child devices emit one unique 10-bit stream
|
|
ID each, but may master through multiple SMMU TBUs */
|
|
iommu-map = <0 &smmu3 0 0x400>;
|
|
|
|
|
|
};
|
|
|
|
- |+
|
|
/* Qcom's arm,smmu-v2 implementation */
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
smmu4: iommu@d00000 {
|
|
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
|
|
reg = <0xd00000 0x10000>;
|
|
|
|
#global-interrupts = <1>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
power-domains = <&mmcc 0>;
|
|
|
|
clocks = <&mmcc 123>,
|
|
<&mmcc 124>;
|
|
clock-names = "bus", "iface";
|
|
};
|