mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-30 13:03:01 +00:00
ed651979bb
Add ACLINT-SSWI variant for the MIPS P8700 SoC. This CPU has a SSWI device compliant with the RISC-V draft spec (see [1]). CPU indexes on this platform are not continuous, instead it uses bit-fields to encode hart,core,cluster numbers, thus the DT property "riscv,hart-indexes" is mandatory for it. Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/all/20250612143911.3224046-4-vladimir.kondratiev@mobileye.com Link: https://github.com/riscvarchive/riscv-aclint [1]
105 lines
2.5 KiB
YAML
105 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: ACLINT Supervisor-level Software Interrupt Device
|
|
|
|
maintainers:
|
|
- Inochi Amaoto <inochiama@outlook.com>
|
|
|
|
description:
|
|
The SSWI device is a part of the ACLINT device. It provides
|
|
supervisor-level IPI functionality for a set of HARTs on a supported
|
|
platforms. It provides a register to set an IPI (SETSSIP) for each
|
|
HART connected to the SSWI device. See draft specification
|
|
https://github.com/riscvarchive/riscv-aclint
|
|
|
|
Following variants of the SSWI ACLINT supported, using dedicated
|
|
compatible string
|
|
- THEAD C900
|
|
- MIPS P8700
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- items:
|
|
- enum:
|
|
- sophgo,sg2044-aclint-sswi
|
|
- const: thead,c900-aclint-sswi
|
|
- items:
|
|
- const: mips,p8700-aclint-sswi
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
"#interrupt-cells":
|
|
const: 0
|
|
|
|
interrupt-controller: true
|
|
|
|
interrupts-extended:
|
|
minItems: 1
|
|
maxItems: 4095
|
|
|
|
riscv,hart-indexes:
|
|
$ref: /schemas/types.yaml#/definitions/uint32-array
|
|
minItems: 1
|
|
maxItems: 4095
|
|
description:
|
|
A list of hart indexes that APLIC should use to address each hart
|
|
that is mentioned in the "interrupts-extended"
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- "#interrupt-cells"
|
|
- interrupt-controller
|
|
- interrupts-extended
|
|
|
|
allOf:
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
const: mips,p8700-aclint-sswi
|
|
then:
|
|
required:
|
|
- riscv,hart-indexes
|
|
else:
|
|
properties:
|
|
riscv,hart-indexes: false
|
|
|
|
examples:
|
|
- |
|
|
//Example 1
|
|
interrupt-controller@94000000 {
|
|
compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
|
|
reg = <0x94000000 0x00004000>;
|
|
#interrupt-cells = <0>;
|
|
interrupt-controller;
|
|
interrupts-extended = <&cpu1intc 1>,
|
|
<&cpu2intc 1>,
|
|
<&cpu3intc 1>,
|
|
<&cpu4intc 1>;
|
|
};
|
|
|
|
- |
|
|
//Example 2
|
|
interrupt-controller@94000000 {
|
|
compatible = "mips,p8700-aclint-sswi";
|
|
reg = <0x94000000 0x00004000>;
|
|
#interrupt-cells = <0>;
|
|
interrupt-controller;
|
|
interrupts-extended = <&cpu1intc 1>,
|
|
<&cpu2intc 1>,
|
|
<&cpu3intc 1>,
|
|
<&cpu4intc 1>;
|
|
riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
|
|
};
|
|
|
|
...
|