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9665ca7a7c
Convert the Synopsys DW-APB interrupt controller binding to schema format. It's a straight-forward conversion of the typical interrupt controller. Link: https://lore.kernel.org/r/20250505144842.1292840-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
65 lines
1.7 KiB
YAML
65 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/snps,dw-apb-ictl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare APB interrupt controller
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maintainers:
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- Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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- Zhen Lei <thunder.leizhen@huawei.com>
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description:
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Synopsys DesignWare provides interrupt controller IP for APB known as
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dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs
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with APB bus, e.g. Marvell Armada 1500. It can also be used as primary
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interrupt controller in some SoCs, e.g. Hisilicon SD5203.
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properties:
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compatible:
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const: snps,dw-apb-ictl
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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interrupts:
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maxItems: 1
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description: >
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Interrupt input connected to the primary interrupt controller when used
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as a secondary controller. The interrupt specifier maps to bits in the
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low and high interrupt registers (0⇒bit 0 low, 1⇒bit 1 low, 32⇒bit 0 high,
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33⇒bit 1 high, fast interrupts start at 64).
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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interrupt-controller@3000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x3000 0xc00>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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- |
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interrupt-controller@10130000 {
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compatible = "snps,dw-apb-ictl";
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reg = <0x10130000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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