mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-30 21:52:21 +00:00
43d78445da
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230320233928.2920693-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
65 lines
1.3 KiB
YAML
65 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Microsemi Ocelot SoC ICPU Interrupt Controller
|
|
|
|
maintainers:
|
|
- Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
|
|
allOf:
|
|
- $ref: /schemas/interrupt-controller.yaml#
|
|
|
|
description: |
|
|
the Microsemi Ocelot interrupt controller that is part of the
|
|
ICPU. It is connected directly to the MIPS core interrupt
|
|
controller.
|
|
|
|
properties:
|
|
compatible:
|
|
items:
|
|
- enum:
|
|
- mscc,jaguar2-icpu-intr
|
|
- mscc,luton-icpu-intr
|
|
- mscc,ocelot-icpu-intr
|
|
- mscc,serval-icpu-intr
|
|
|
|
|
|
'#interrupt-cells':
|
|
const: 1
|
|
|
|
'#address-cells':
|
|
const: 0
|
|
|
|
interrupt-controller: true
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- '#interrupt-cells'
|
|
- '#address-cells'
|
|
- interrupt-controller
|
|
- reg
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
intc: interrupt-controller@70000070 {
|
|
compatible = "mscc,ocelot-icpu-intr";
|
|
reg = <0x70000070 0x70>;
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
};
|
|
...
|