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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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f7e642bcd6
Convert the marvell,mpic device-tree binding to YAML. Add myself as maintainer. Signed-off-by: Marek Behún <kabel@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240624145355.8034-3-kabel@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
64 lines
1.5 KiB
YAML
64 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada 370, 375, 38x, 39x, XP Interrupt Controller
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maintainers:
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- Marek Behún <kabel@kernel.org>
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description: |
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The top-level interrupt controller on Marvell Armada 370 and XP. On these
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platforms it also provides inter-processor interrupts.
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On Marvell Armada 375, 38x and 39x this controller is wired under ARM GIC.
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Provides MSI handling for the PCIe controllers.
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properties:
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compatible:
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const: marvell,mpic
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reg:
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items:
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- description: main registers
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- description: per-cpu registers
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interrupts:
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items:
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- description: |
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Parent interrupt on platforms where MPIC is not the top-level
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interrupt controller.
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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msi-controller: true
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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- msi-controller
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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interrupt-controller@20a00 {
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compatible = "marvell,mpic";
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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msi-controller;
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};
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