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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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57e464a30d
i.MX8qxp Display Controller has a built-in interrupt controller to support Enable/Status/Preset/Clear interrupt bit. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414035028.1561475-8-victor.liu@nxp.com
319 lines
11 KiB
YAML
319 lines
11 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX8qxp Display Controller interrupt controller
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description: |
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The Display Controller has a built-in interrupt controller with the following
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features for all relevant HW events:
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* Enable bit (mask)
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* Status bit (set by an HW event)
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* Preset bit (can be used by SW to set status)
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* Clear bit (used by SW to reset the status)
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Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
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Alternatively the un-masked trigger signals for all HW events are provided,
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allowing it to use a global interrupt controller instead.
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Each interrupt can be protected against SW running in user mode. In that case,
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only privileged AHB access can control the interrupt status.
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maintainers:
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- Liu Ying <victor.liu@nxp.com>
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properties:
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compatible:
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const: fsl,imx8qxp-dc-intc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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interrupts:
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items:
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- description: store9 shadow load interrupt(blit engine)
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- description: store9 frame complete interrupt(blit engine)
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- description: store9 sequence complete interrupt(blit engine)
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- description:
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extdst0 shadow load interrupt
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(display controller, content stream 0)
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- description:
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extdst0 frame complete interrupt
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(display controller, content stream 0)
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- description:
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extdst0 sequence complete interrupt
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(display controller, content stream 0)
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- description:
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extdst4 shadow load interrupt
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(display controller, safety stream 0)
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- description:
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extdst4 frame complete interrupt
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(display controller, safety stream 0)
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- description:
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extdst4 sequence complete interrupt
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(display controller, safety stream 0)
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- description:
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extdst1 shadow load interrupt
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(display controller, content stream 1)
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- description:
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extdst1 frame complete interrupt
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(display controller, content stream 1)
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- description:
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extdst1 sequence complete interrupt
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(display controller, content stream 1)
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- description:
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extdst5 shadow load interrupt
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(display controller, safety stream 1)
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- description:
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extdst5 frame complete interrupt
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(display controller, safety stream 1)
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- description:
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extdst5 sequence complete interrupt
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(display controller, safety stream 1)
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- description:
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disengcfg0 shadow load interrupt
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(display controller, display stream 0)
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- description:
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disengcfg0 frame complete interrupt
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(display controller, display stream 0)
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- description:
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disengcfg0 sequence complete interrupt
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(display controller, display stream 0)
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- description:
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framegen0 programmable interrupt0
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(display controller, display stream 0)
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- description:
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framegen0 programmable interrupt1
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(display controller, display stream 0)
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- description:
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framegen0 programmable interrupt2
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(display controller, display stream 0)
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- description:
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framegen0 programmable interrupt3
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(display controller, display stream 0)
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- description:
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signature0 shadow load interrupt
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(display controller, display stream 0)
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- description:
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signature0 measurement valid interrupt
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(display controller, display stream 0)
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- description:
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signature0 error condition interrupt
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(display controller, display stream 0)
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- description:
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disengcfg1 shadow load interrupt
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(display controller, display stream 1)
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- description:
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disengcfg1 frame complete interrupt
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(display controller, display stream 1)
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- description:
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disengcfg1 sequence complete interrupt
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(display controller, display stream 1)
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- description:
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framegen1 programmable interrupt0
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(display controller, display stream 1)
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- description:
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framegen1 programmable interrupt1
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(display controller, display stream 1)
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- description:
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framegen1 programmable interrupt2
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(display controller, display stream 1)
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- description:
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framegen1 programmable interrupt3
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(display controller, display stream 1)
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- description:
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signature1 shadow load interrupt
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(display controller, display stream 1)
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- description:
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signature1 measurement valid interrupt
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(display controller, display stream 1)
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- description:
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signature1 error condition interrupt
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(display controller, display stream 1)
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- description: reserved
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- description:
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command sequencer error condition interrupt(command sequencer)
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- description:
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common control software interrupt0(common control)
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- description:
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common control software interrupt1(common control)
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- description:
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common control software interrupt2(common control)
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- description:
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common control software interrupt3(common control)
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- description:
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framegen0 synchronization status activated interrupt
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(display controller, safety stream 0)
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- description:
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framegen0 synchronization status deactivated interrupt
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(display controller, safety stream 0)
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- description:
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framegen0 synchronization status activated interrupt
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(display controller, content stream 0)
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- description:
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framegen0 synchronization status deactivated interrupt
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(display controller, content stream 0)
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- description:
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framegen1 synchronization status activated interrupt
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(display controller, safety stream 1)
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- description:
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framegen1 synchronization status deactivated interrupt
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(display controller, safety stream 1)
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- description:
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framegen1 synchronization status activated interrupt
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(display controller, content stream 1)
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- description:
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framegen1 synchronization status deactivated interrupt
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(display controller, content stream 1)
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minItems: 49
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interrupt-names:
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items:
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- const: store9_shdload
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- const: store9_framecomplete
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- const: store9_seqcomplete
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- const: extdst0_shdload
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- const: extdst0_framecomplete
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- const: extdst0_seqcomplete
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- const: extdst4_shdload
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- const: extdst4_framecomplete
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- const: extdst4_seqcomplete
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- const: extdst1_shdload
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- const: extdst1_framecomplete
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- const: extdst1_seqcomplete
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- const: extdst5_shdload
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- const: extdst5_framecomplete
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- const: extdst5_seqcomplete
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- const: disengcfg_shdload0
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- const: disengcfg_framecomplete0
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- const: disengcfg_seqcomplete0
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- const: framegen0_int0
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- const: framegen0_int1
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- const: framegen0_int2
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- const: framegen0_int3
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- const: sig0_shdload
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- const: sig0_valid
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- const: sig0_error
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- const: disengcfg_shdload1
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- const: disengcfg_framecomplete1
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- const: disengcfg_seqcomplete1
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- const: framegen1_int0
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- const: framegen1_int1
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- const: framegen1_int2
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- const: framegen1_int3
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- const: sig1_shdload
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- const: sig1_valid
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- const: sig1_error
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- const: reserved
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- const: cmdseq_error
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- const: comctrl_sw0
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- const: comctrl_sw1
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- const: comctrl_sw2
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- const: comctrl_sw3
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- const: framegen0_primsync_on
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- const: framegen0_primsync_off
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- const: framegen0_secsync_on
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- const: framegen0_secsync_off
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- const: framegen1_primsync_on
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- const: framegen1_primsync_off
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- const: framegen1_secsync_on
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- const: framegen1_secsync_off
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minItems: 49
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required:
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- compatible
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- reg
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- clocks
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- interrupt-controller
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- "#interrupt-cells"
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8-lpcg.h>
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interrupt-controller@56180040 {
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compatible = "fsl,imx8qxp-dc-intc";
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reg = <0x56180040 0x60>;
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clocks = <&dc0_lpcg IMX_LPCG_CLK_5>;
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interrupt-controller;
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interrupt-parent = <&dc0_irqsteer>;
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#interrupt-cells = <1>;
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interrupts = <448>, <449>, <450>, <64>,
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<65>, <66>, <67>, <68>,
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<69>, <70>, <193>, <194>,
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<195>, <196>, <197>, <72>,
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<73>, <74>, <75>, <76>,
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<77>, <78>, <79>, <80>,
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<81>, <199>, <200>, <201>,
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<202>, <203>, <204>, <205>,
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<206>, <207>, <208>, <5>,
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<0>, <1>, <2>, <3>,
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<4>, <82>, <83>, <84>,
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<85>, <209>, <210>, <211>,
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<212>;
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interrupt-names = "store9_shdload",
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"store9_framecomplete",
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"store9_seqcomplete",
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"extdst0_shdload",
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"extdst0_framecomplete",
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"extdst0_seqcomplete",
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"extdst4_shdload",
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"extdst4_framecomplete",
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"extdst4_seqcomplete",
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"extdst1_shdload",
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"extdst1_framecomplete",
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"extdst1_seqcomplete",
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"extdst5_shdload",
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"extdst5_framecomplete",
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"extdst5_seqcomplete",
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"disengcfg_shdload0",
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"disengcfg_framecomplete0",
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"disengcfg_seqcomplete0",
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"framegen0_int0",
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"framegen0_int1",
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"framegen0_int2",
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"framegen0_int3",
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"sig0_shdload",
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"sig0_valid",
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"sig0_error",
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"disengcfg_shdload1",
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"disengcfg_framecomplete1",
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"disengcfg_seqcomplete1",
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"framegen1_int0",
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"framegen1_int1",
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"framegen1_int2",
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"framegen1_int3",
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"sig1_shdload",
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"sig1_valid",
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"sig1_error",
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"reserved",
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"cmdseq_error",
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"comctrl_sw0",
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"comctrl_sw1",
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"comctrl_sw2",
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"comctrl_sw3",
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"framegen0_primsync_on",
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"framegen0_primsync_off",
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"framegen0_secsync_on",
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"framegen0_secsync_off",
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"framegen1_primsync_on",
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"framegen1_primsync_off",
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"framegen1_secsync_on",
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"framegen1_secsync_off";
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};
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