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9e65863194
Document and describe the compatibles for Apple A7-A11 SoCs. There are three feature levels: - apple,aic: No fast IPI, for A7-A10 - apple,t8015-aic: fast IPI, global only, for A11 - apple,t8103-aic: fast IPI with local and global support, for M1 Each feature level is an extension of the previous, for example, M1 will also work with the A7 feature level. All of A7-M1 gets its own SoC-specific compatible, and the "apple,aic" compatible as a fallback. Signed-off-by: Nick Chan <towinchenmi@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Sven Peter <sven@svenpeter.dev> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/all/20240901034143.12731-2-towinchenmi@gmail.com
134 lines
3.7 KiB
YAML
134 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Apple Interrupt Controller
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maintainers:
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- Hector Martin <marcan@marcan.st>
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description: |
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The Apple Interrupt Controller is a simple interrupt controller present on
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Apple ARM SoC platforms, including various iPhone and iPad devices and the
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"Apple Silicon" Macs.
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It provides the following features:
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- Level-triggered hardware IRQs wired to SoC blocks
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- Single mask bit per IRQ
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- Per-IRQ affinity setting
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- Automatic masking on event delivery (auto-ack)
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- Software triggering (ORed with hw line)
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- 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
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if not symmetric)
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- Automatic prioritization (single event/ack register per CPU, lower IRQs =
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higher priority)
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- Automatic masking on ack
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- Default "this CPU" register view and explicit per-CPU views
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This device also represents the FIQ interrupt sources on platforms using AIC,
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which do not go through a discrete interrupt controller.
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IPIs may be performed via MMIO registers on all variants of AIC. Starting
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from A11, system registers may also be used for "fast" IPIs. Starting from
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M1, even faster IPIs within the same cluster may be achieved by writing to
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a "local" fast IPI register as opposed to using the "global" fast IPI
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register.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- apple,s5l8960x-aic
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- apple,t7000-aic
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- apple,s8000-aic
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- apple,t8010-aic
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- apple,t8015-aic
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- apple,t8103-aic
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- const: apple,aic
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interrupt-controller: true
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'#interrupt-cells':
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const: 3
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description: |
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The 1st cell contains the interrupt type:
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- 0: Hardware IRQ
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- 1: FIQ
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The 2nd cell contains the interrupt number.
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- HW IRQs: interrupt number
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- FIQs:
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- 0: physical HV timer
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- 1: virtual HV timer
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- 2: physical guest timer
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- 3: virtual guest timer
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- 4: 'efficient' CPU PMU
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- 5: 'performance' CPU PMU
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The 3rd cell contains the interrupt flags. This is normally
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IRQ_TYPE_LEVEL_HIGH (4).
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reg:
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description: |
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Specifies base physical address and size of the AIC registers.
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maxItems: 1
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power-domains:
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maxItems: 1
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affinities:
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type: object
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additionalProperties: false
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description:
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FIQ affinity can be expressed as a single "affinities" node,
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containing a set of sub-nodes, one per FIQ with a non-default
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affinity.
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patternProperties:
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"^.+-affinity$":
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type: object
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additionalProperties: false
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properties:
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apple,fiq-index:
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description:
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The interrupt number specified as a FIQ, and for which
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the affinity is not the default.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 5
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cpus:
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description:
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Should be a list of phandles to CPU nodes (as described in
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Documentation/devicetree/bindings/arm/cpus.yaml).
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required:
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- apple,fiq-index
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- cpus
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required:
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- compatible
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- '#interrupt-cells'
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- interrupt-controller
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- reg
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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aic: interrupt-controller@23b100000 {
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compatible = "apple,t8103-aic", "apple,aic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x2 0x3b100000 0x0 0x8000>;
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};
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};
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